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[RISCV][SDAG] Add pre-commit tests. NFC.
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‎llvm/test/CodeGen/RISCV/select.ll

Lines changed: 281 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1626,3 +1626,284 @@ define i32 @select_cst_unknown(i32 signext %a, i32 signext %b) {
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%ret = select i1 %cond, i32 5, i32 -7
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ret i32 %ret
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}
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define i32 @select_cst1(i1 zeroext %cond) {
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; RV32IM-LABEL: select_cst1:
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; RV32IM: # %bb.0:
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; RV32IM-NEXT: mv a1, a0
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; RV32IM-NEXT: li a0, 10
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; RV32IM-NEXT: bnez a1, .LBB43_2
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; RV32IM-NEXT: # %bb.1:
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; RV32IM-NEXT: li a0, 20
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; RV32IM-NEXT: .LBB43_2:
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; RV32IM-NEXT: ret
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;
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; RV64IM-LABEL: select_cst1:
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; RV64IM: # %bb.0:
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; RV64IM-NEXT: mv a1, a0
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; RV64IM-NEXT: li a0, 10
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; RV64IM-NEXT: bnez a1, .LBB43_2
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; RV64IM-NEXT: # %bb.1:
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; RV64IM-NEXT: li a0, 20
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; RV64IM-NEXT: .LBB43_2:
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; RV64IM-NEXT: ret
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;
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; RV64IMXVTCONDOPS-LABEL: select_cst1:
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; RV64IMXVTCONDOPS: # %bb.0:
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; RV64IMXVTCONDOPS-NEXT: li a1, 20
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; RV64IMXVTCONDOPS-NEXT: vt.maskcn a1, a1, a0
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; RV64IMXVTCONDOPS-NEXT: li a2, 10
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; RV64IMXVTCONDOPS-NEXT: vt.maskc a0, a2, a0
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; RV64IMXVTCONDOPS-NEXT: or a0, a0, a1
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; RV64IMXVTCONDOPS-NEXT: ret
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;
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; CHECKZICOND-LABEL: select_cst1:
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; CHECKZICOND: # %bb.0:
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; CHECKZICOND-NEXT: li a1, 20
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; CHECKZICOND-NEXT: czero.nez a1, a1, a0
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; CHECKZICOND-NEXT: li a2, 10
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; CHECKZICOND-NEXT: czero.eqz a0, a2, a0
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; CHECKZICOND-NEXT: or a0, a0, a1
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; CHECKZICOND-NEXT: ret
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%ret = select i1 %cond, i32 10, i32 20
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ret i32 %ret
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}
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define i32 @select_cst2(i1 zeroext %cond) {
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; RV32IM-LABEL: select_cst2:
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; RV32IM: # %bb.0:
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; RV32IM-NEXT: mv a1, a0
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; RV32IM-NEXT: li a0, 10
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; RV32IM-NEXT: bnez a1, .LBB44_2
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; RV32IM-NEXT: # %bb.1:
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; RV32IM-NEXT: lui a0, 5
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; RV32IM-NEXT: addi a0, a0, -480
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; RV32IM-NEXT: .LBB44_2:
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; RV32IM-NEXT: ret
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;
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; RV64IM-LABEL: select_cst2:
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; RV64IM: # %bb.0:
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; RV64IM-NEXT: mv a1, a0
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; RV64IM-NEXT: li a0, 10
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; RV64IM-NEXT: bnez a1, .LBB44_2
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; RV64IM-NEXT: # %bb.1:
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; RV64IM-NEXT: lui a0, 5
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; RV64IM-NEXT: addiw a0, a0, -480
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; RV64IM-NEXT: .LBB44_2:
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; RV64IM-NEXT: ret
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;
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; RV64IMXVTCONDOPS-LABEL: select_cst2:
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; RV64IMXVTCONDOPS: # %bb.0:
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; RV64IMXVTCONDOPS-NEXT: li a1, 10
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; RV64IMXVTCONDOPS-NEXT: vt.maskc a1, a1, a0
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; RV64IMXVTCONDOPS-NEXT: lui a2, 5
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; RV64IMXVTCONDOPS-NEXT: addiw a2, a2, -480
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; RV64IMXVTCONDOPS-NEXT: vt.maskcn a0, a2, a0
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; RV64IMXVTCONDOPS-NEXT: or a0, a1, a0
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; RV64IMXVTCONDOPS-NEXT: ret
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;
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; RV32IMZICOND-LABEL: select_cst2:
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; RV32IMZICOND: # %bb.0:
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; RV32IMZICOND-NEXT: li a1, 10
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; RV32IMZICOND-NEXT: czero.eqz a1, a1, a0
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; RV32IMZICOND-NEXT: lui a2, 5
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; RV32IMZICOND-NEXT: addi a2, a2, -480
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; RV32IMZICOND-NEXT: czero.nez a0, a2, a0
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; RV32IMZICOND-NEXT: or a0, a1, a0
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; RV32IMZICOND-NEXT: ret
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;
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; RV64IMZICOND-LABEL: select_cst2:
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; RV64IMZICOND: # %bb.0:
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; RV64IMZICOND-NEXT: li a1, 10
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; RV64IMZICOND-NEXT: czero.eqz a1, a1, a0
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; RV64IMZICOND-NEXT: lui a2, 5
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; RV64IMZICOND-NEXT: addiw a2, a2, -480
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; RV64IMZICOND-NEXT: czero.nez a0, a2, a0
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; RV64IMZICOND-NEXT: or a0, a1, a0
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; RV64IMZICOND-NEXT: ret
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%ret = select i1 %cond, i32 10, i32 20000
1725+
ret i32 %ret
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}
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define i32 @select_cst3(i1 zeroext %cond) {
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; RV32IM-LABEL: select_cst3:
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; RV32IM: # %bb.0:
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; RV32IM-NEXT: bnez a0, .LBB45_2
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; RV32IM-NEXT: # %bb.1:
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; RV32IM-NEXT: lui a0, 5
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; RV32IM-NEXT: addi a0, a0, -480
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; RV32IM-NEXT: ret
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; RV32IM-NEXT: .LBB45_2:
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; RV32IM-NEXT: lui a0, 7
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; RV32IM-NEXT: addi a0, a0, 1328
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; RV32IM-NEXT: ret
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;
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; RV64IM-LABEL: select_cst3:
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; RV64IM: # %bb.0:
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; RV64IM-NEXT: bnez a0, .LBB45_2
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; RV64IM-NEXT: # %bb.1:
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; RV64IM-NEXT: lui a0, 5
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; RV64IM-NEXT: addiw a0, a0, -480
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; RV64IM-NEXT: ret
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; RV64IM-NEXT: .LBB45_2:
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; RV64IM-NEXT: lui a0, 7
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; RV64IM-NEXT: addiw a0, a0, 1328
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; RV64IM-NEXT: ret
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;
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; RV64IMXVTCONDOPS-LABEL: select_cst3:
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; RV64IMXVTCONDOPS: # %bb.0:
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; RV64IMXVTCONDOPS-NEXT: lui a1, 5
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; RV64IMXVTCONDOPS-NEXT: addiw a1, a1, -480
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; RV64IMXVTCONDOPS-NEXT: vt.maskcn a1, a1, a0
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; RV64IMXVTCONDOPS-NEXT: lui a2, 7
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; RV64IMXVTCONDOPS-NEXT: addiw a2, a2, 1328
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; RV64IMXVTCONDOPS-NEXT: vt.maskc a0, a2, a0
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; RV64IMXVTCONDOPS-NEXT: or a0, a0, a1
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; RV64IMXVTCONDOPS-NEXT: ret
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;
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; RV32IMZICOND-LABEL: select_cst3:
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; RV32IMZICOND: # %bb.0:
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; RV32IMZICOND-NEXT: lui a1, 5
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; RV32IMZICOND-NEXT: addi a1, a1, -480
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; RV32IMZICOND-NEXT: czero.nez a1, a1, a0
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; RV32IMZICOND-NEXT: lui a2, 7
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; RV32IMZICOND-NEXT: addi a2, a2, 1328
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; RV32IMZICOND-NEXT: czero.eqz a0, a2, a0
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; RV32IMZICOND-NEXT: or a0, a0, a1
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; RV32IMZICOND-NEXT: ret
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;
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; RV64IMZICOND-LABEL: select_cst3:
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; RV64IMZICOND: # %bb.0:
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; RV64IMZICOND-NEXT: lui a1, 5
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; RV64IMZICOND-NEXT: addiw a1, a1, -480
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; RV64IMZICOND-NEXT: czero.nez a1, a1, a0
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; RV64IMZICOND-NEXT: lui a2, 7
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; RV64IMZICOND-NEXT: addiw a2, a2, 1328
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; RV64IMZICOND-NEXT: czero.eqz a0, a2, a0
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; RV64IMZICOND-NEXT: or a0, a0, a1
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; RV64IMZICOND-NEXT: ret
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%ret = select i1 %cond, i32 30000, i32 20000
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ret i32 %ret
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}
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define i32 @select_cst4(i1 zeroext %cond) {
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; CHECK-LABEL: select_cst4:
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; CHECK: # %bb.0:
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; CHECK-NEXT: neg a0, a0
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; CHECK-NEXT: xori a0, a0, 2047
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; CHECK-NEXT: ret
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%ret = select i1 %cond, i32 -2048, i32 2047
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ret i32 %ret
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}
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define i32 @select_cst5(i1 zeroext %cond) {
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; RV32IM-LABEL: select_cst5:
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; RV32IM: # %bb.0:
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; RV32IM-NEXT: mv a1, a0
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; RV32IM-NEXT: li a0, 2047
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; RV32IM-NEXT: bnez a1, .LBB47_2
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; RV32IM-NEXT: # %bb.1:
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; RV32IM-NEXT: lui a0, 1
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; RV32IM-NEXT: addi a0, a0, -2047
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; RV32IM-NEXT: .LBB47_2:
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; RV32IM-NEXT: ret
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;
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; RV64IM-LABEL: select_cst5:
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; RV64IM: # %bb.0:
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; RV64IM-NEXT: mv a1, a0
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; RV64IM-NEXT: li a0, 2047
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; RV64IM-NEXT: bnez a1, .LBB47_2
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; RV64IM-NEXT: # %bb.1:
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; RV64IM-NEXT: lui a0, 1
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; RV64IM-NEXT: addiw a0, a0, -2047
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; RV64IM-NEXT: .LBB47_2:
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; RV64IM-NEXT: ret
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;
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; RV64IMXVTCONDOPS-LABEL: select_cst5:
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; RV64IMXVTCONDOPS: # %bb.0:
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; RV64IMXVTCONDOPS-NEXT: li a1, 2047
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; RV64IMXVTCONDOPS-NEXT: vt.maskc a1, a1, a0
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; RV64IMXVTCONDOPS-NEXT: lui a2, 1
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; RV64IMXVTCONDOPS-NEXT: addiw a2, a2, -2047
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; RV64IMXVTCONDOPS-NEXT: vt.maskcn a0, a2, a0
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; RV64IMXVTCONDOPS-NEXT: or a0, a1, a0
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; RV64IMXVTCONDOPS-NEXT: ret
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;
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; RV32IMZICOND-LABEL: select_cst5:
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; RV32IMZICOND: # %bb.0:
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; RV32IMZICOND-NEXT: li a1, 2047
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; RV32IMZICOND-NEXT: czero.eqz a1, a1, a0
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; RV32IMZICOND-NEXT: lui a2, 1
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; RV32IMZICOND-NEXT: addi a2, a2, -2047
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; RV32IMZICOND-NEXT: czero.nez a0, a2, a0
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; RV32IMZICOND-NEXT: or a0, a1, a0
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; RV32IMZICOND-NEXT: ret
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;
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; RV64IMZICOND-LABEL: select_cst5:
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; RV64IMZICOND: # %bb.0:
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; RV64IMZICOND-NEXT: li a1, 2047
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; RV64IMZICOND-NEXT: czero.eqz a1, a1, a0
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; RV64IMZICOND-NEXT: lui a2, 1
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; RV64IMZICOND-NEXT: addiw a2, a2, -2047
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; RV64IMZICOND-NEXT: czero.nez a0, a2, a0
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; RV64IMZICOND-NEXT: or a0, a1, a0
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; RV64IMZICOND-NEXT: ret
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%ret = select i1 %cond, i32 2047, i32 2049
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ret i32 %ret
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}
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define i32 @select_cst6(i1 zeroext %cond) {
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; RV32IM-LABEL: select_cst6:
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; RV32IM: # %bb.0:
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; RV32IM-NEXT: bnez a0, .LBB48_2
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; RV32IM-NEXT: # %bb.1:
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; RV32IM-NEXT: li a0, 2047
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; RV32IM-NEXT: ret
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; RV32IM-NEXT: .LBB48_2:
1863+
; RV32IM-NEXT: lui a0, 1
1864+
; RV32IM-NEXT: addi a0, a0, -2047
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; RV32IM-NEXT: ret
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;
1867+
; RV64IM-LABEL: select_cst6:
1868+
; RV64IM: # %bb.0:
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; RV64IM-NEXT: bnez a0, .LBB48_2
1870+
; RV64IM-NEXT: # %bb.1:
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; RV64IM-NEXT: li a0, 2047
1872+
; RV64IM-NEXT: ret
1873+
; RV64IM-NEXT: .LBB48_2:
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; RV64IM-NEXT: lui a0, 1
1875+
; RV64IM-NEXT: addiw a0, a0, -2047
1876+
; RV64IM-NEXT: ret
1877+
;
1878+
; RV64IMXVTCONDOPS-LABEL: select_cst6:
1879+
; RV64IMXVTCONDOPS: # %bb.0:
1880+
; RV64IMXVTCONDOPS-NEXT: li a1, 2047
1881+
; RV64IMXVTCONDOPS-NEXT: vt.maskcn a1, a1, a0
1882+
; RV64IMXVTCONDOPS-NEXT: lui a2, 1
1883+
; RV64IMXVTCONDOPS-NEXT: addiw a2, a2, -2047
1884+
; RV64IMXVTCONDOPS-NEXT: vt.maskc a0, a2, a0
1885+
; RV64IMXVTCONDOPS-NEXT: or a0, a0, a1
1886+
; RV64IMXVTCONDOPS-NEXT: ret
1887+
;
1888+
; RV32IMZICOND-LABEL: select_cst6:
1889+
; RV32IMZICOND: # %bb.0:
1890+
; RV32IMZICOND-NEXT: li a1, 2047
1891+
; RV32IMZICOND-NEXT: czero.nez a1, a1, a0
1892+
; RV32IMZICOND-NEXT: lui a2, 1
1893+
; RV32IMZICOND-NEXT: addi a2, a2, -2047
1894+
; RV32IMZICOND-NEXT: czero.eqz a0, a2, a0
1895+
; RV32IMZICOND-NEXT: or a0, a0, a1
1896+
; RV32IMZICOND-NEXT: ret
1897+
;
1898+
; RV64IMZICOND-LABEL: select_cst6:
1899+
; RV64IMZICOND: # %bb.0:
1900+
; RV64IMZICOND-NEXT: li a1, 2047
1901+
; RV64IMZICOND-NEXT: czero.nez a1, a1, a0
1902+
; RV64IMZICOND-NEXT: lui a2, 1
1903+
; RV64IMZICOND-NEXT: addiw a2, a2, -2047
1904+
; RV64IMZICOND-NEXT: czero.eqz a0, a2, a0
1905+
; RV64IMZICOND-NEXT: or a0, a0, a1
1906+
; RV64IMZICOND-NEXT: ret
1907+
%ret = select i1 %cond, i32 2049, i32 2047
1908+
ret i32 %ret
1909+
}

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