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[AMDGPU] Don't optimize agpr phis if the operand doesn't have subreg use (#91267)
If the operand doesn't have any subreg use, the optimization could potentially generate `V_ACCVGPR_READ_B32_e64` with wrong register class. The following example demonstrates the issue. Input MIR: ``` bb.0: %0:sgpr_32 = S_MOV_B32 0 %1:sgpr_128 = REG_SEQUENCE %0:sgpr_32, %subreg.sub0, %0:sgpr_32, %subreg.sub1, %0:sgpr_32, %subreg.sub2, %0:sgpr_32, %subreg.sub3 %2:vreg_128 = COPY %1:sgpr_128 %3:areg_128 = COPY %2:vreg_128, implicit $exec bb.1: %4:areg_128 = PHI %3:areg_128, %bb.0, %6:areg_128, %bb.1 %5:areg_128 = PHI %3:areg_128, %bb.0, %7:areg_128, %bb.1 ... ``` Output of current implementation: ``` bb.0: %0:agpr_32 = V_ACCVGPR_WRITE_B32_e64 0, implicit $exec %1:agpr_32 = V_ACCVGPR_WRITE_B32_e64 0, implicit $exec %2:agpr_32 = V_ACCVGPR_WRITE_B32_e64 0, implicit $exec %3:agpr_32 = V_ACCVGPR_WRITE_B32_e64 0, implicit $exec %4:areg_128 = REG_SEQUENCE %0:agpr_32, %subreg.sub0, %1:agpr_32, %subreg.sub1, %2:agpr_32, %subreg.sub2, %3:agpr_32, %subreg.sub3 %5:vreg_128 = V_ACCVGPR_READ_B32_e64 %4:areg_128, implicit $exec %6:areg_128 = COPY %46:vreg_128 bb.1: %7:areg_128 = PHI %6:areg_128, %bb.0, %9:areg_128, %bb.1 %8:areg_128 = PHI %6:areg_128, %bb.0, %10:areg_128, %bb.1 ... ``` The problem is the generated `V_ACCVGPR_READ_B32_e64` instruction. Apparently the operand `%4:areg_128` is not valid for this. In this patch, we don't count the none-subreg use because `V_ACCVGPR_READ_B32_e64` can't handle none-32-bit operand. Fixes: SWDEV-459556
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‎llvm/lib/Target/AMDGPU/SIFoldOperands.cpp

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@@ -2106,6 +2106,8 @@ bool SIFoldOperands::tryOptimizeAGPRPhis(MachineBasicBlock &MBB) {
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for (unsigned K = 1; K < MI.getNumOperands(); K += 2) {
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MachineOperand &PhiMO = MI.getOperand(K);
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if (!PhiMO.getSubReg())
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continue;
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RegToMO[{PhiMO.getReg(), PhiMO.getSubReg()}].push_back(&PhiMO);
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}
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}

‎llvm/test/CodeGen/AMDGPU/fold-agpr-phis.mir

Lines changed: 82 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -465,7 +465,6 @@ body: |
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; GFX90A-NEXT: bb.2:
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; GFX90A-NEXT: S_ENDPGM 0
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bb.0:
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; Tests that tryOptimizeAGPRPhis kicks in for GFX908.
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liveins: $sgpr0, $scc
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successors: %bb.1
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@@ -715,3 +714,85 @@ body: |
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bb.3:
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S_ENDPGM 0
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...
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---
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name: skip_optimize_agpr_phi_without_subreg_use
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tracksRegLiveness: true
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body: |
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; GFX908-LABEL: name: skip_optimize_agpr_phi_without_subreg_use
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; GFX908: bb.0:
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; GFX908-NEXT: successors: %bb.1(0x80000000)
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; GFX908-NEXT: liveins: $scc
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; GFX908-NEXT: {{ $}}
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; GFX908-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
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; GFX908-NEXT: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 0
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; GFX908-NEXT: [[V_ACCVGPR_WRITE_B32_e64_:%[0-9]+]]:agpr_32 = V_ACCVGPR_WRITE_B32_e64 0, implicit $exec
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; GFX908-NEXT: [[V_ACCVGPR_WRITE_B32_e64_1:%[0-9]+]]:agpr_32 = V_ACCVGPR_WRITE_B32_e64 0, implicit $exec
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; GFX908-NEXT: [[V_ACCVGPR_WRITE_B32_e64_2:%[0-9]+]]:agpr_32 = V_ACCVGPR_WRITE_B32_e64 0, implicit $exec
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; GFX908-NEXT: [[V_ACCVGPR_WRITE_B32_e64_3:%[0-9]+]]:agpr_32 = V_ACCVGPR_WRITE_B32_e64 0, implicit $exec
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; GFX908-NEXT: [[REG_SEQUENCE:%[0-9]+]]:areg_128_align2 = REG_SEQUENCE [[V_ACCVGPR_WRITE_B32_e64_]], %subreg.sub0, [[V_ACCVGPR_WRITE_B32_e64_1]], %subreg.sub1, [[V_ACCVGPR_WRITE_B32_e64_2]], %subreg.sub2, [[V_ACCVGPR_WRITE_B32_e64_3]], %subreg.sub3
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; GFX908-NEXT: {{ $}}
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; GFX908-NEXT: bb.1:
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; GFX908-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; GFX908-NEXT: liveins: $scc
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; GFX908-NEXT: {{ $}}
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; GFX908-NEXT: [[PHI:%[0-9]+]]:areg_128_align2 = PHI [[REG_SEQUENCE]], %bb.0, %7, %bb.1
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; GFX908-NEXT: [[V_MFMA_F32_16X16X4F32_e64_:%[0-9]+]]:areg_128_align2 = V_MFMA_F32_16X16X4F32_e64 [[V_MOV_B32_e32_]], [[V_MOV_B32_e32_]], [[PHI]], 0, 0, 0, implicit $mode, implicit $exec
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; GFX908-NEXT: [[COPY:%[0-9]+]]:areg_128_align2 = COPY [[V_MFMA_F32_16X16X4F32_e64_]], implicit $exec
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; GFX908-NEXT: S_CBRANCH_SCC1 %bb.1, implicit $scc
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; GFX908-NEXT: {{ $}}
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; GFX908-NEXT: bb.2:
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; GFX908-NEXT: S_ENDPGM 0
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;
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; GFX90A-LABEL: name: skip_optimize_agpr_phi_without_subreg_use
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; GFX90A: bb.0:
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; GFX90A-NEXT: successors: %bb.1(0x80000000)
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; GFX90A-NEXT: liveins: $scc
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; GFX90A-NEXT: {{ $}}
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; GFX90A-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
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; GFX90A-NEXT: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 0
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; GFX90A-NEXT: [[V_ACCVGPR_WRITE_B32_e64_:%[0-9]+]]:agpr_32 = V_ACCVGPR_WRITE_B32_e64 0, implicit $exec
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; GFX90A-NEXT: [[V_ACCVGPR_WRITE_B32_e64_1:%[0-9]+]]:agpr_32 = V_ACCVGPR_WRITE_B32_e64 0, implicit $exec
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; GFX90A-NEXT: [[V_ACCVGPR_WRITE_B32_e64_2:%[0-9]+]]:agpr_32 = V_ACCVGPR_WRITE_B32_e64 0, implicit $exec
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; GFX90A-NEXT: [[V_ACCVGPR_WRITE_B32_e64_3:%[0-9]+]]:agpr_32 = V_ACCVGPR_WRITE_B32_e64 0, implicit $exec
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; GFX90A-NEXT: [[REG_SEQUENCE:%[0-9]+]]:areg_128_align2 = REG_SEQUENCE [[V_ACCVGPR_WRITE_B32_e64_]], %subreg.sub0, [[V_ACCVGPR_WRITE_B32_e64_1]], %subreg.sub1, [[V_ACCVGPR_WRITE_B32_e64_2]], %subreg.sub2, [[V_ACCVGPR_WRITE_B32_e64_3]], %subreg.sub3
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; GFX90A-NEXT: {{ $}}
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; GFX90A-NEXT: bb.1:
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; GFX90A-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; GFX90A-NEXT: liveins: $scc
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; GFX90A-NEXT: {{ $}}
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; GFX90A-NEXT: [[PHI:%[0-9]+]]:areg_128_align2 = PHI [[REG_SEQUENCE]], %bb.0, %7, %bb.1
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; GFX90A-NEXT: [[V_MFMA_F32_16X16X4F32_e64_:%[0-9]+]]:areg_128_align2 = V_MFMA_F32_16X16X4F32_e64 [[V_MOV_B32_e32_]], [[V_MOV_B32_e32_]], [[PHI]], 0, 0, 0, implicit $mode, implicit $exec
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; GFX90A-NEXT: [[COPY:%[0-9]+]]:areg_128_align2 = COPY [[V_MFMA_F32_16X16X4F32_e64_]], implicit $exec
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; GFX90A-NEXT: S_CBRANCH_SCC1 %bb.1, implicit $scc
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; GFX90A-NEXT: {{ $}}
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; GFX90A-NEXT: bb.2:
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; GFX90A-NEXT: S_ENDPGM 0
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bb.0:
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liveins: $scc
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successors: %bb.1
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%0:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
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%1:sgpr_32 = S_MOV_B32 0
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%2:sgpr_128 = REG_SEQUENCE %1, %subreg.sub0, %1, %subreg.sub1, %1, %subreg.sub2, %1, %subreg.sub3
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%3:vreg_128 = COPY %2
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%4:sreg_64 = S_MOV_B64 0
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%5:areg_128_align2 = COPY %3, implicit $exec
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bb.1:
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liveins: $scc
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successors: %bb.1, %bb.2
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%9:areg_128_align2 = PHI %5, %bb.0, %10, %bb.1
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%11:areg_128_align2 = V_MFMA_F32_16X16X4F32_e64 %0:vgpr_32, %0:vgpr_32, %9:areg_128_align2, 0, 0, 0, implicit $mode, implicit $exec
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%12:vgpr_32 = COPY %11.sub3
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%13:vgpr_32 = COPY %11.sub2
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%14:vgpr_32 = COPY %11.sub1
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%15:vgpr_32 = COPY %11.sub0
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%10:areg_128_align2 = COPY %11, implicit $exec
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S_CBRANCH_SCC1 %bb.1, implicit $scc
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bb.2:
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S_ENDPGM 0
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...

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