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michaelmaitlandmichaelmaitland
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[RISCV] Add sifive-p470 processor (#102022)
This is an OOO core that has a vector unit. For more information see https://www.sifive.com/cores/performance-p450-470. Use the existing P400 scheduler model. This model is missing accurate vector scheduling support, but it will be added in a follow up patch. Other tunings can come in future patches too.
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‎clang/test/Driver/riscv-cpus.c

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// MCPU-SIFIVE-P450-SAME: "-target-feature" "+zbs"
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// MCPU-SIFIVE-P450-SAME: "-target-abi" "lp64d"
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// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-p470 | FileCheck -check-prefix=MCPU-SIFIVE-P470 %s
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// MCPU-SIFIVE-P470: "-target-cpu" "sifive-p470"
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// MCPU-SIFIVE-P470-SAME: "-target-feature" "+m"
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// MCPU-SIFIVE-P470-SAME: "-target-feature" "+a"
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// MCPU-SIFIVE-P470-SAME: "-target-feature" "+f"
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// MCPU-SIFIVE-P470-SAME: "-target-feature" "+d"
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// MCPU-SIFIVE-P470-SAME: "-target-feature" "+c"
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// MCPU-SIFIVE-P470-SAME: "-target-feature" "+v"
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// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zic64b"
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// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zicbom"
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// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zicbop"
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// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zicboz"
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// MCPU-SIFIVE-P470-SAME: "-target-feature" "+ziccamoa"
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// MCPU-SIFIVE-P470-SAME: "-target-feature" "+ziccif"
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// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zicclsm"
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// MCPU-SIFIVE-P470-SAME: "-target-feature" "+ziccrse"
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// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zicsr"
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// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zifencei"
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// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zihintntl"
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// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zihintpause"
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// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zihpm"
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// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zmmul"
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// MCPU-SIFIVE-P470-SAME: "-target-feature" "+za64rs"
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// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zfhmin"
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// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zba"
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// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zbb"
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// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zbs"
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// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zvbb"
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// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zvbc"
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// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zve32f"
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// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zve32x"
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// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zve64d"
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// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zve64f"
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// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zve64x"
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// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zvkg"
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// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zvkn"
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// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zvknc"
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// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zvkned"
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// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zvkng"
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// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zvknhb"
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// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zvks"
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// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zvksc"
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// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zvksed"
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// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zvksg"
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// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zvksh"
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// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zvkt"
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// MCPU-SIFIVE-P470-SAME: "-target-abi" "lp64d"
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// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-p670 | FileCheck -check-prefix=MCPU-SIFIVE-P670 %s
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// MCPU-SIFIVE-P670: "-target-cpu" "sifive-p670"
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// MCPU-SIFIVE-P670-SAME: "-target-feature" "+m"

‎clang/test/Misc/target-invalid-cpu-note.c

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// RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix RISCV64
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// RISCV64: error: unknown target CPU 'not-a-cpu'
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// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, spacemit-x60, syntacore-scr3-rv64, syntacore-scr4-rv64, veyron-v1, xiangshan-nanhu{{$}}
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// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-p450, sifive-p470, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, spacemit-x60, syntacore-scr3-rv64, syntacore-scr4-rv64, veyron-v1, xiangshan-nanhu{{$}}
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// RUN: not %clang_cc1 -triple riscv32 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV32
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// TUNE-RISCV32: error: unknown target CPU 'not-a-cpu'
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// TUNE-RISCV32-NEXT: note: valid target CPU values are: generic-rv32, rocket-rv32, sifive-e20, sifive-e21, sifive-e24, sifive-e31, sifive-e34, sifive-e76, syntacore-scr1-base, syntacore-scr1-max, syntacore-scr3-rv32, syntacore-scr4-rv32, generic, rocket, sifive-7-series{{$}}
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// RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV64
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// TUNE-RISCV64: error: unknown target CPU 'not-a-cpu'
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// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, spacemit-x60, syntacore-scr3-rv64, syntacore-scr4-rv64, veyron-v1, xiangshan-nanhu, generic, rocket, sifive-7-series{{$}}
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// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-p450, sifive-p470, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, spacemit-x60, syntacore-scr3-rv64, syntacore-scr4-rv64, veyron-v1, xiangshan-nanhu, generic, rocket, sifive-7-series{{$}}
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‎llvm/docs/ReleaseNotes.rst

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the required alignment space with a sequence of `0x0` bytes (the requested
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fill value) rather than NOPs.
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* Added Syntacore SCR4 CPUs: ``-mcpu=syntacore-scr4-rv32/64``
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* ``-mcpu=sifive-p470`` was added.
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Changes to the WebAssembly Backend
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----------------------------------

‎llvm/lib/Target/RISCV/RISCVProcessors.td

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@@ -239,6 +239,12 @@ def SIFIVE_X280 : RISCVProcessorModel<"sifive-x280", SiFive7Model,
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FeatureStdExtZbb],
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SiFiveX280TuneFeatures>;
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defvar SiFiveP400TuneFeatures = [TuneNoDefaultUnroll,
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TuneConditionalCompressedMoveFusion,
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TuneLUIADDIFusion,
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TuneAUIPCADDIFusion,
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FeaturePostRAScheduler];
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def SIFIVE_P450 : RISCVProcessorModel<"sifive-p450", SiFiveP400Model,
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[Feature64Bit,
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FeatureStdExtI,
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FeatureStdExtZfhmin,
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FeatureUnalignedScalarMem,
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FeatureUnalignedVectorMem],
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[TuneNoDefaultUnroll,
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TuneConditionalCompressedMoveFusion,
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TuneLUIADDIFusion,
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TuneAUIPCADDIFusion,
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FeaturePostRAScheduler]>;
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SiFiveP400TuneFeatures>;
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def SIFIVE_P470 : RISCVProcessorModel<"sifive-p470", SiFiveP400Model,
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!listconcat(RVA22U64Features,
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[FeatureStdExtV,
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FeatureStdExtZifencei,
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FeatureStdExtZihintntl,
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FeatureStdExtZvl128b,
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FeatureStdExtZvbb,
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FeatureStdExtZvknc,
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FeatureStdExtZvkng,
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FeatureStdExtZvksc,
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FeatureStdExtZvksg,
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FeatureVendorXSiFivecdiscarddlone,
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FeatureVendorXSiFivecflushdlone,
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FeatureUnalignedScalarMem,
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FeatureUnalignedVectorMem]),
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!listconcat(SiFiveP400TuneFeatures,
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[TuneNoSinkSplatOperands])>;
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def SIFIVE_P670 : RISCVProcessorModel<"sifive-p670", SiFiveP600Model,
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[Feature64Bit,

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