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Add SME2 Z-t b16-to-b16 intrinsics under sve-b161b6
- Predicate the SME2 Z-targeting b16-to-b16 intrinsics under FEAT_SME2, FEAT_SVE_B16B16. - Add tests in ./clang/test/Sema/aarch64-sme2-intrinsics/acle_sme2_b16b16.cpp to verify this change. - Combine streaming/non-streaming SVE mode tests into a single file, ./clang/test/Sema/aarch4-sve2p1-intrinsics/acle_sve2p1_b16b16. - Delete ./clang/test/Sema/aarch64-sve2p1-intrinsics/acle_sve2p1_b16b16_streaming.cpp (redundant).
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4 files changed

+69
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‎clang/include/clang/Basic/arm_sve.td

Lines changed: 23 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -2116,7 +2116,7 @@ def SVFCLAMP_BF : SInst<"svclamp[_{d}]", "dddd", "b", MergeNone, "aarch64_sve_
21162116
multiclass MinMaxIntr<string i, string zm, string mul, string t> {
21172117
def SVS # NAME : SInst<"sv" # i # "[" # zm # "_{d}_" # mul # "]", t, "csil", MergeNone, "aarch64_sve_s" # i # zm # "_" # mul, [IsStreaming], []>;
21182118
def SVU # NAME : SInst<"sv" # i # "[" # zm # "_{d}_" # mul # "]", t, "UcUsUiUl", MergeNone, "aarch64_sve_u" # i # zm # "_" # mul, [IsStreaming], []>;
2119-
def SVF # NAME : SInst<"sv" # i # "[" # zm # "_{d}_" # mul # "]", t, "bhfd", MergeNone, "aarch64_sve_f" # i # zm # "_" # mul, [IsStreaming], []>;
2119+
def SVF # NAME : SInst<"sv" # i # "[" # zm # "_{d}_" # mul # "]", t, "hfd", MergeNone, "aarch64_sve_f" # i # zm # "_" # mul, [IsStreaming], []>;
21202120
}
21212121

21222122
let SVETargetGuard = InvalidMode, SMETargetGuard = "sme2" in {
@@ -2134,11 +2134,11 @@ let SVETargetGuard = InvalidMode, SMETargetGuard = "sme2" in {
21342134
}
21352135

21362136
multiclass SInstMinMaxByVector<string name> {
2137-
def NAME # _SINGLE_X2 : SInst<"sv" # name # "nm[_single_{d}_x2]", "22d", "bhfd", MergeNone, "aarch64_sve_f" # name # "nm_single_x2", [IsStreaming], []>;
2138-
def NAME # _SINGLE_X4 : SInst<"sv" # name # "nm[_single_{d}_x4]", "44d", "bhfd", MergeNone, "aarch64_sve_f" # name # "nm_single_x4", [IsStreaming], []>;
2137+
def NAME # _SINGLE_X2 : SInst<"sv" # name # "nm[_single_{d}_x2]", "22d", "hfd", MergeNone, "aarch64_sve_f" # name # "nm_single_x2", [IsStreaming], []>;
2138+
def NAME # _SINGLE_X4 : SInst<"sv" # name # "nm[_single_{d}_x4]", "44d", "hfd", MergeNone, "aarch64_sve_f" # name # "nm_single_x4", [IsStreaming], []>;
21392139

2140-
def NAME # _X2 : SInst<"sv" # name # "nm[_{d}_x2]", "222", "bhfd", MergeNone, "aarch64_sve_f" # name # "nm_x2", [IsStreaming], []>;
2141-
def NAME # _X4 : SInst<"sv" # name # "nm[_{d}_x4]", "444", "bhfd", MergeNone, "aarch64_sve_f" # name # "nm_x4", [IsStreaming], []>;
2140+
def NAME # _X2 : SInst<"sv" # name # "nm[_{d}_x2]", "222", "hfd", MergeNone, "aarch64_sve_f" # name # "nm_x2", [IsStreaming], []>;
2141+
def NAME # _X4 : SInst<"sv" # name # "nm[_{d}_x4]", "444", "hfd", MergeNone, "aarch64_sve_f" # name # "nm_x4", [IsStreaming], []>;
21422142
}
21432143

21442144
let SVETargetGuard = InvalidMode, SMETargetGuard = "sme2" in {
@@ -2172,9 +2172,25 @@ let SVETargetGuard = InvalidMode, SMETargetGuard = "sme2" in {
21722172
def SVFCLAMP_X4 : SInst<"svclamp[_single_{d}_x4]", "44dd", "hfd", MergeNone, "aarch64_sve_fclamp_single_x4", [IsStreaming], []>;
21732173
}
21742174

2175+
multiclass BfSingleMultiVector<string name> {
2176+
def NAME # _SINGLE_X2 : SInst<"sv" # name # "[_single_{d}_x2]", "22d", "b", MergeNone, "aarch64_sve_f" # name # "_single_x2", [IsStreaming], []>;
2177+
def NAME # _SINGLE_X4 : SInst<"sv" # name # "[_single_{d}_x4]", "44d", "b", MergeNone, "aarch64_sve_f" # name # "_single_x4", [IsStreaming], []>;
2178+
2179+
def NAME # _X2 : SInst<"sv" # name # "[_{d}_x2]", "222", "b", MergeNone, "aarch64_sve_f" # name # "_x2", [IsStreaming], []>;
2180+
def NAME # _X4 : SInst<"sv" # name # "[_{d}_x4]", "444", "b", MergeNone, "aarch64_sve_f" # name # "_x4", [IsStreaming], []>;
2181+
}
2182+
21752183
let SVETargetGuard = InvalidMode, SMETargetGuard = "sme2,sve-b16b16"in {
2176-
def SVBFCLAMP_X2 : SInst<"svclamp[_single_{d}_x2]", "22dd", "b", MergeNone, "aarch64_sve_bfclamp_single_x2", [IsStreaming], []>;
2177-
def SVBFCLAMP_X4 : SInst<"svclamp[_single_{d}_x4]", "44dd", "b", MergeNone, "aarch64_sve_bfclamp_single_x4", [IsStreaming], []>;
2184+
def SVBFCLAMP_X2 : SInst<"svclamp[_single_{d}_x2]", "22dd", "b", MergeNone, "aarch64_sve_bfclamp_single_x2", [IsStreaming], []>;
2185+
def SVBFCLAMP_X4 : SInst<"svclamp[_single_{d}_x4]", "44dd", "b", MergeNone, "aarch64_sve_bfclamp_single_x4", [IsStreaming], []>;
2186+
2187+
// bfmin, bfmax (single, multi)
2188+
defm SVBFMIN : BfSingleMultiVector<"min">;
2189+
defm SVBFMAX : BfSingleMultiVector<"max">;
2190+
2191+
// bfminnm, bfmaxnm (single, multi)
2192+
defm SVBFMINNM : BfSingleMultiVector<"minnm">;
2193+
defm SVBFMAXNM : BfSingleMultiVector<"maxnm">;
21782194
}
21792195

21802196
let SVETargetGuard = InvalidMode, SMETargetGuard = "sme2" in {

‎clang/test/Sema/aarch64-sme2-intrinsics/acle_sme2_b16b16.cpp

Lines changed: 37 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -10,4 +10,41 @@ void test_b16b16( svbfloat16_t bf16, svbfloat16x2_t bf16x2, svbfloat16x4_t bf16x
1010
svclamp_single_bf16_x2(bf16x2, bf16, bf16);
1111
// expected-error@+1 {{'svclamp_single_bf16_x4' needs target feature sme2,sve-b16b16}}
1212
svclamp_single_bf16_x4(bf16x4, bf16, bf16);
13+
14+
// expected-error@+1 {{'svmax_single_bf16_x2' needs target feature sme2,sve-b16b16}}
15+
svmax_single_bf16_x2(bf16x2, bf16);
16+
// expected-error@+1 {{'svmax_single_bf16_x4' needs target feature sme2,sve-b16b16}}
17+
svmax_single_bf16_x4(bf16x4, bf16);
18+
// expected-error@+1 {{'svmax_bf16_x2' needs target feature sme2,sve-b16b16}}
19+
svmax_bf16_x2(bf16x2, bf16x2);
20+
// expected-error@+1 {{'svmax_bf16_x4' needs target feature sme2,sve-b16b16}}
21+
svmax_bf16_x4(bf16x4, bf16x4);
22+
23+
// expected-error@+1 {{'svmaxnm_single_bf16_x2' needs target feature sme2,sve-b16b16}}
24+
svmaxnm_single_bf16_x2(bf16x2, bf16);
25+
// expected-error@+1 {{'svmaxnm_single_bf16_x4' needs target feature sme2,sve-b16b16}}
26+
svmaxnm_single_bf16_x4(bf16x4, bf16);
27+
// expected-error@+1 {{'svmaxnm_bf16_x2' needs target feature sme2,sve-b16b16}}
28+
svmaxnm_bf16_x2(bf16x2, bf16x2);
29+
// expected-error@+1 {{'svmaxnm_bf16_x4' needs target feature sme2,sve-b16b16}}
30+
svmaxnm_bf16_x4(bf16x4, bf16x4);
31+
32+
// expected-error@+1 {{'svmin_single_bf16_x2' needs target feature sme2,sve-b16b16}}
33+
svmin_single_bf16_x2(bf16x2, bf16);
34+
// expected-error@+1 {{'svmin_single_bf16_x4' needs target feature sme2,sve-b16b16}}
35+
svmin_single_bf16_x4(bf16x4, bf16);
36+
// expected-error@+1 {{'svmin_bf16_x2' needs target feature sme2,sve-b16b16}}
37+
svmin_bf16_x2(bf16x2, bf16x2);
38+
// expected-error@+1 {{'svmin_bf16_x4' needs target feature sme2,sve-b16b16}}
39+
svmin_bf16_x4(bf16x4, bf16x4);
40+
41+
// expected-error@+1 {{'svminnm_single_bf16_x2' needs target feature sme2,sve-b16b16}}
42+
svminnm_single_bf16_x2(bf16x2, bf16);
43+
// expected-error@+1 {{'svminnm_single_bf16_x4' needs target feature sme2,sve-b16b16}}
44+
svminnm_single_bf16_x4(bf16x4, bf16);
45+
46+
// expected-error@+1 {{'svminnm_bf16_x2' needs target feature sme2,sve-b16b16}}
47+
svminnm_bf16_x2(bf16x2, bf16x2);
48+
// expected-error@+1 {{'svminnm_bf16_x4' needs target feature sme2,sve-b16b16}}
49+
svminnm_bf16_x4(bf16x4, bf16x4);
1350
}

‎clang/test/Sema/aarch64-sve2p1-intrinsics/acle_sve2p1_b16b16.cpp

Lines changed: 9 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,10 +1,17 @@
11
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -verify -verify-ignore-unexpected=error,note -emit-llvm -o - %s
2+
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -verify -verify-ignore-unexpected=error,note -emit-llvm -o - %s
23
// REQUIRES: aarch64-registered-target
34

45
#include <arm_sve.h>
56

7+
#if defined __ARM_FEATURE_SME
8+
#define MODE_ATTR __arm_streaming
9+
#else
10+
#define MODE_ATTR
11+
#endif
12+
613
__attribute__((target("sve-b16b16")))
7-
void test_with_b16b16(svbool_t pg, svbfloat16_t op1, svbfloat16_t op2, svbfloat16_t op3)
14+
void test_with_sve_b16b16(svbool_t pg, svbfloat16_t op1, svbfloat16_t op2, svbfloat16_t op3) MODE_ATTR
815
{
916
svclamp_bf16(op1, op2, op3);
1017
svadd_bf16_m(pg, op1, op2);
@@ -20,7 +27,7 @@ void test_with_b16b16(svbool_t pg, svbfloat16_t op1, svbfloat16_t op2, svbfloat1
2027
svsub_bf16_m(pg, op1, op2);
2128
}
2229

23-
void test_no_b16b16(svbool_t pg, svbfloat16_t op1, svbfloat16_t op2, svbfloat16_t op3)
30+
void test_no_sve_b16b16(svbool_t pg, svbfloat16_t op1, svbfloat16_t op2, svbfloat16_t op3) MODE_ATTR
2431
{
2532
// expected-error@+1 {{'svclamp_bf16' needs target feature (sve2,sve-b16b16)|(sme2,sve-b16b16)}}
2633
svclamp_bf16(op1, op2, op3);

‎clang/test/Sema/aarch64-sve2p1-intrinsics/acle_sve2p1_b16b16_streaming.cpp

Lines changed: 0 additions & 50 deletions
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