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wangpc-ppwangpc-pp
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[RISCV] Run mem2reg to simplify Zbc tests (#70169)
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  • clang/test/CodeGen/RISCV/rvb-intrinsics

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‎clang/test/CodeGen/RISCV/rvb-intrinsics/zbc.c

Lines changed: 16 additions & 56 deletions
Original file line numberDiff line numberDiff line change
@@ -1,52 +1,36 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
22
// RUN: %clang_cc1 -triple riscv32 -target-feature +zbc -emit-llvm %s -o - \
3+
// RUN: -disable-O0-optnone | opt -S -passes=mem2reg \
34
// RUN: | FileCheck %s -check-prefix=RV32ZBC
45
// RUN: %clang_cc1 -triple riscv64 -target-feature +zbc -emit-llvm %s -o - \
6+
// RUN: -disable-O0-optnone | opt -S -passes=mem2reg \
57
// RUN: | FileCheck %s -check-prefix=RV64ZBC
68

79
#include <stdint.h>
810

911
#if __riscv_xlen == 64
1012
// RV64ZBC-LABEL: @clmul_64(
1113
// RV64ZBC-NEXT: entry:
12-
// RV64ZBC-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
13-
// RV64ZBC-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
14-
// RV64ZBC-NEXT: store i64 [[A:%.*]], ptr [[A_ADDR]], align 8
15-
// RV64ZBC-NEXT: store i64 [[B:%.*]], ptr [[B_ADDR]], align 8
16-
// RV64ZBC-NEXT: [[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8
17-
// RV64ZBC-NEXT: [[TMP1:%.*]] = load i64, ptr [[B_ADDR]], align 8
18-
// RV64ZBC-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.clmul.i64(i64 [[TMP0]], i64 [[TMP1]])
19-
// RV64ZBC-NEXT: ret i64 [[TMP2]]
14+
// RV64ZBC-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.clmul.i64(i64 [[A:%.*]], i64 [[B:%.*]])
15+
// RV64ZBC-NEXT: ret i64 [[TMP0]]
2016
//
2117
uint64_t clmul_64(uint64_t a, uint64_t b) {
2218
return __builtin_riscv_clmul_64(a, b);
2319
}
2420

2521
// RV64ZBC-LABEL: @clmulh_64(
2622
// RV64ZBC-NEXT: entry:
27-
// RV64ZBC-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
28-
// RV64ZBC-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
29-
// RV64ZBC-NEXT: store i64 [[A:%.*]], ptr [[A_ADDR]], align 8
30-
// RV64ZBC-NEXT: store i64 [[B:%.*]], ptr [[B_ADDR]], align 8
31-
// RV64ZBC-NEXT: [[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8
32-
// RV64ZBC-NEXT: [[TMP1:%.*]] = load i64, ptr [[B_ADDR]], align 8
33-
// RV64ZBC-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.clmulh.i64(i64 [[TMP0]], i64 [[TMP1]])
34-
// RV64ZBC-NEXT: ret i64 [[TMP2]]
23+
// RV64ZBC-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.clmulh.i64(i64 [[A:%.*]], i64 [[B:%.*]])
24+
// RV64ZBC-NEXT: ret i64 [[TMP0]]
3525
//
3626
uint64_t clmulh_64(uint64_t a, uint64_t b) {
3727
return __builtin_riscv_clmulh_64(a, b);
3828
}
3929

4030
// RV64ZBC-LABEL: @clmulr_64(
4131
// RV64ZBC-NEXT: entry:
42-
// RV64ZBC-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
43-
// RV64ZBC-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
44-
// RV64ZBC-NEXT: store i64 [[A:%.*]], ptr [[A_ADDR]], align 8
45-
// RV64ZBC-NEXT: store i64 [[B:%.*]], ptr [[B_ADDR]], align 8
46-
// RV64ZBC-NEXT: [[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8
47-
// RV64ZBC-NEXT: [[TMP1:%.*]] = load i64, ptr [[B_ADDR]], align 8
48-
// RV64ZBC-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.clmulr.i64(i64 [[TMP0]], i64 [[TMP1]])
49-
// RV64ZBC-NEXT: ret i64 [[TMP2]]
32+
// RV64ZBC-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.clmulr.i64(i64 [[A:%.*]], i64 [[B:%.*]])
33+
// RV64ZBC-NEXT: ret i64 [[TMP0]]
5034
//
5135
uint64_t clmulr_64(uint64_t a, uint64_t b) {
5236
return __builtin_riscv_clmulr_64(a, b);
@@ -55,25 +39,13 @@ uint64_t clmulr_64(uint64_t a, uint64_t b) {
5539

5640
// RV32ZBC-LABEL: @clmul_32(
5741
// RV32ZBC-NEXT: entry:
58-
// RV32ZBC-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
59-
// RV32ZBC-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
60-
// RV32ZBC-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
61-
// RV32ZBC-NEXT: store i32 [[B:%.*]], ptr [[B_ADDR]], align 4
62-
// RV32ZBC-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
63-
// RV32ZBC-NEXT: [[TMP1:%.*]] = load i32, ptr [[B_ADDR]], align 4
64-
// RV32ZBC-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.clmul.i32(i32 [[TMP0]], i32 [[TMP1]])
65-
// RV32ZBC-NEXT: ret i32 [[TMP2]]
42+
// RV32ZBC-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.clmul.i32(i32 [[A:%.*]], i32 [[B:%.*]])
43+
// RV32ZBC-NEXT: ret i32 [[TMP0]]
6644
//
6745
// RV64ZBC-LABEL: @clmul_32(
6846
// RV64ZBC-NEXT: entry:
69-
// RV64ZBC-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
70-
// RV64ZBC-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
71-
// RV64ZBC-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
72-
// RV64ZBC-NEXT: store i32 [[B:%.*]], ptr [[B_ADDR]], align 4
73-
// RV64ZBC-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
74-
// RV64ZBC-NEXT: [[TMP1:%.*]] = load i32, ptr [[B_ADDR]], align 4
75-
// RV64ZBC-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.clmul.i32(i32 [[TMP0]], i32 [[TMP1]])
76-
// RV64ZBC-NEXT: ret i32 [[TMP2]]
47+
// RV64ZBC-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.clmul.i32(i32 [[A:%.*]], i32 [[B:%.*]])
48+
// RV64ZBC-NEXT: ret i32 [[TMP0]]
7749
//
7850
uint32_t clmul_32(uint32_t a, uint32_t b) {
7951
return __builtin_riscv_clmul_32(a, b);
@@ -82,29 +54,17 @@ uint32_t clmul_32(uint32_t a, uint32_t b) {
8254
#if __riscv_xlen == 32
8355
// RV32ZBC-LABEL: @clmulh_32(
8456
// RV32ZBC-NEXT: entry:
85-
// RV32ZBC-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
86-
// RV32ZBC-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
87-
// RV32ZBC-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
88-
// RV32ZBC-NEXT: store i32 [[B:%.*]], ptr [[B_ADDR]], align 4
89-
// RV32ZBC-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
90-
// RV32ZBC-NEXT: [[TMP1:%.*]] = load i32, ptr [[B_ADDR]], align 4
91-
// RV32ZBC-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.clmulh.i32(i32 [[TMP0]], i32 [[TMP1]])
92-
// RV32ZBC-NEXT: ret i32 [[TMP2]]
57+
// RV32ZBC-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.clmulh.i32(i32 [[A:%.*]], i32 [[B:%.*]])
58+
// RV32ZBC-NEXT: ret i32 [[TMP0]]
9359
//
9460
uint32_t clmulh_32(uint32_t a, uint32_t b) {
9561
return __builtin_riscv_clmulh_32(a, b);
9662
}
9763

9864
// RV32ZBC-LABEL: @clmulr_32(
9965
// RV32ZBC-NEXT: entry:
100-
// RV32ZBC-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
101-
// RV32ZBC-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
102-
// RV32ZBC-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
103-
// RV32ZBC-NEXT: store i32 [[B:%.*]], ptr [[B_ADDR]], align 4
104-
// RV32ZBC-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
105-
// RV32ZBC-NEXT: [[TMP1:%.*]] = load i32, ptr [[B_ADDR]], align 4
106-
// RV32ZBC-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.clmulr.i32(i32 [[TMP0]], i32 [[TMP1]])
107-
// RV32ZBC-NEXT: ret i32 [[TMP2]]
66+
// RV32ZBC-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.clmulr.i32(i32 [[A:%.*]], i32 [[B:%.*]])
67+
// RV32ZBC-NEXT: ret i32 [[TMP0]]
10868
//
10969
uint32_t clmulr_32(uint32_t a, uint32_t b) {
11070
return __builtin_riscv_clmulr_32(a, b);

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