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[MC] Add MCRegister::isPhysical. NFC
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3 files changed

+10
-7
lines changed

3 files changed

+10
-7
lines changed

llvm/include/llvm/MC/MCRegister.h

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -68,6 +68,10 @@ class MCRegister {
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return FirstPhysicalReg <= Reg && Reg < FirstStackSlot;
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}
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/// Return true if the specified register number is in the physical register
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/// namespace.
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constexpr bool isPhysical() const { return isPhysicalRegister(Reg); }
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constexpr operator unsigned() const { return Reg; }
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/// Check the provided unsigned value is a valid MCRegister.

llvm/include/llvm/MC/MCRegisterInfo.h

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -530,7 +530,7 @@ class MCSubRegIterator
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MCSubRegIterator(MCRegister Reg, const MCRegisterInfo *MCRI,
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bool IncludeSelf = false) {
533-
assert(MCRegister::isPhysicalRegister(Reg.id()));
533+
assert(Reg.isPhysical());
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I.init(Reg.id(), MCRI->DiffLists + MCRI->get(Reg).SubRegs);
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// Initially, the iterator points to Reg itself.
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Val = MCPhysReg(*I);
@@ -600,7 +600,7 @@ class MCSuperRegIterator
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MCSuperRegIterator(MCRegister Reg, const MCRegisterInfo *MCRI,
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bool IncludeSelf = false) {
603-
assert(MCRegister::isPhysicalRegister(Reg.id()));
603+
assert(Reg.isPhysical());
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I.init(Reg.id(), MCRI->DiffLists + MCRI->get(Reg).SuperRegs);
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// Initially, the iterator points to Reg itself.
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Val = MCPhysReg(*I);
@@ -646,8 +646,7 @@ class MCRegUnitIterator
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MCRegUnitIterator() = default;
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MCRegUnitIterator(MCRegister Reg, const MCRegisterInfo *MCRI) {
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assert(Reg && "Null register has no regunits");
650-
assert(MCRegister::isPhysicalRegister(Reg.id()));
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assert(Reg.isPhysical());
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// Decode the RegUnits MCRegisterDesc field.
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unsigned RU = MCRI->get(Reg).RegUnits;
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unsigned FirstRU = RU & ((1u << RegUnitBits) - 1);

llvm/utils/TableGen/AsmMatcherEmitter.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -2522,9 +2522,9 @@ static void emitValidateOperandClass(const CodeGenTarget &Target,
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for (auto &MatchClassName : Table)
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OS << " " << MatchClassName << ",\n";
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OS << " };\n\n";
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OS << " unsigned RegID = Operand.getReg().id();\n";
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OS << " MatchClassKind OpKind = MCRegister::isPhysicalRegister(RegID) ? "
2527-
"(MatchClassKind)Table[RegID] : InvalidMatchClass;\n";
2525+
OS << " MCRegister Reg = Operand.getReg();\n";
2526+
OS << " MatchClassKind OpKind = Reg.isPhysical() ? "
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"(MatchClassKind)Table[Reg.id()] : InvalidMatchClass;\n";
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OS << " return isSubclass(OpKind, Kind) ? "
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<< "(unsigned)MCTargetAsmParser::Match_Success :\n "
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<< " getDiagKindFromRegisterClass(Kind);\n }\n\n";

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