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jakeeganjakeegan
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Revert "[PowerPC] Add error for incorrect use of memory operands (#114277)"
This commit broke a test on a couple bots lld :: ELF/ppc64-local-exec-tls.s This reverts commit 9358905.
1 parent 6ade03d commit 0e52a07

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11 files changed

+25
-82
lines changed

11 files changed

+25
-82
lines changed

‎llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp

Lines changed: 2 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,6 @@
88

99
#include "MCTargetDesc/PPCMCExpr.h"
1010
#include "MCTargetDesc/PPCMCTargetDesc.h"
11-
#include "PPCInstrInfo.h"
1211
#include "PPCTargetStreamer.h"
1312
#include "TargetInfo/PowerPCTargetInfo.h"
1413
#include "llvm/ADT/STLExtras.h"
@@ -183,7 +182,6 @@ struct PPCOperand : public MCParsedAsmOperand {
183182

184183
struct ImmOp {
185184
int64_t Val;
186-
bool IsMemOpBase;
187185
};
188186

189187
struct ExprOp {
@@ -244,9 +242,6 @@ struct PPCOperand : public MCParsedAsmOperand {
244242
/// isPPC64 - True if this operand is for an instruction in 64-bit mode.
245243
bool isPPC64() const { return IsPPC64; }
246244

247-
/// isMemOpBase - True if this operand is the base of a memory operand.
248-
bool isMemOpBase() const { return Kind == Immediate && Imm.IsMemOpBase; }
249-
250245
int64_t getImm() const {
251246
assert(Kind == Immediate && "Invalid access!");
252247
return Imm.Val;
@@ -699,11 +694,9 @@ struct PPCOperand : public MCParsedAsmOperand {
699694
}
700695

701696
static std::unique_ptr<PPCOperand> CreateImm(int64_t Val, SMLoc S, SMLoc E,
702-
bool IsPPC64,
703-
bool IsMemOpBase = false) {
697+
bool IsPPC64) {
704698
auto Op = std::make_unique<PPCOperand>(Immediate);
705699
Op->Imm.Val = Val;
706-
Op->Imm.IsMemOpBase = IsMemOpBase;
707700
Op->StartLoc = S;
708701
Op->EndLoc = E;
709702
Op->IsPPC64 = IsPPC64;
@@ -1257,29 +1250,14 @@ void PPCAsmParser::processInstruction(MCInst &Inst,
12571250
static std::string PPCMnemonicSpellCheck(StringRef S, const FeatureBitset &FBS,
12581251
unsigned VariantID = 0);
12591252

1260-
// Check that the register+immediate memory operand is in the right position and
1261-
// is expected by the instruction. Returns true if the memory operand syntax is
1262-
// valid; otherwise, returns false.
1263-
static bool validateMemOp(const OperandVector &Operands, bool isMemriOp) {
1264-
for (size_t idx = 0; idx < Operands.size(); ++idx) {
1265-
const PPCOperand &Op = static_cast<const PPCOperand &>(*Operands[idx]);
1266-
if (Op.isMemOpBase() != (idx == 3 && isMemriOp))
1267-
return false;
1268-
}
1269-
return true;
1270-
}
1271-
12721253
bool PPCAsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
12731254
OperandVector &Operands,
12741255
MCStreamer &Out, uint64_t &ErrorInfo,
12751256
bool MatchingInlineAsm) {
12761257
MCInst Inst;
1277-
const PPCInstrInfo *TII = static_cast<const PPCInstrInfo *>(&MII);
12781258

12791259
switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) {
12801260
case Match_Success:
1281-
if (!validateMemOp(Operands, TII->isMemriOp(Inst.getOpcode())))
1282-
return Error(IDLoc, "invalid operand for instruction");
12831261
// Post-process instructions (typically extended mnemonics)
12841262
processInstruction(Inst, Operands);
12851263
Inst.setLoc(IDLoc);
@@ -1637,8 +1615,7 @@ bool PPCAsmParser::parseOperand(OperandVector &Operands) {
16371615
E = Parser.getTok().getLoc();
16381616
if (parseToken(AsmToken::RParen, "missing ')'"))
16391617
return true;
1640-
Operands.push_back(
1641-
PPCOperand::CreateImm(IntVal, S, E, isPPC64(), /*IsMemOpBase=*/true));
1618+
Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
16421619
}
16431620

16441621
return false;

‎llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -171,9 +171,7 @@ enum {
171171
/// This instruction produced a sign extended result.
172172
SExt32To64 = 0x1 << (NewDef_Shift + 2),
173173
/// This instruction produced a zero extended result.
174-
ZExt32To64 = 0x1 << (NewDef_Shift + 3),
175-
/// This instruction takes a register+immediate memory operand.
176-
MemriOp = 0x1 << (NewDef_Shift + 4)
174+
ZExt32To64 = 0x1 << (NewDef_Shift + 3)
177175
};
178176
} // end namespace PPCII
179177

‎llvm/lib/Target/PowerPC/PPCInstr64Bit.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -777,7 +777,7 @@ def ADDIS8 : DForm_2<15, (outs g8rc:$RST), (ins g8rc_nox0:$RA, s17imm64:$D),
777777
def LA8 : DForm_2<14, (outs g8rc:$RST), (ins g8rc_nox0:$RA, s16imm64:$D),
778778
"la $RST, $D($RA)", IIC_IntGeneral,
779779
[(set i64:$RST, (add i64:$RA,
780-
(PPClo tglobaladdr:$D, 0)))]>, MemriOp;
780+
(PPClo tglobaladdr:$D, 0)))]>;
781781

782782
let Defs = [CARRY] in {
783783
def SUBFIC8: DForm_2< 8, (outs g8rc:$RST), (ins g8rc:$RA, s16imm64:$D),

‎llvm/lib/Target/PowerPC/PPCInstrFormats.td

Lines changed: 5 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -55,10 +55,6 @@ class I<bits<6> opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin>
5555
bits<1> ZExt32To64 = 0;
5656
let TSFlags{9} = ZExt32To64;
5757

58-
// Indicate that this instruction takes a register+immediate memory operand.
59-
bits<1> MemriOp = 0;
60-
let TSFlags{10} = MemriOp;
61-
6258
// Fields used for relation models.
6359
string BaseName = "";
6460

@@ -86,7 +82,6 @@ class PPC970_Unit_BRU { bits<3> PPC970_Unit = 7; }
8682
class XFormMemOp { bits<1> XFormMemOp = 1; }
8783
class SExt32To64 { bits<1> SExt32To64 = 1; }
8884
class ZExt32To64 { bits<1> ZExt32To64 = 1; }
89-
class MemriOp { bits<1> MemriOp = 1; }
9085

9186
// Two joined instructions; used to emit two adjacent instructions as one.
9287
// The itinerary from the first instruction is used for scheduling and
@@ -255,7 +250,7 @@ class DForm_base<bits<6> opcode, dag OOL, dag IOL, string asmstr,
255250

256251
class DForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr,
257252
InstrItinClass itin, list<dag> pattern>
258-
: DForm_base<opcode, OOL, IOL, asmstr, itin, pattern>, MemriOp {
253+
: DForm_base<opcode, OOL, IOL, asmstr, itin, pattern> {
259254
}
260255

261256
class DForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr,
@@ -300,7 +295,6 @@ class DForm_4_zero<bits<6> opcode, dag OOL, dag IOL, string asmstr,
300295
let RST = 0;
301296
let RA = 0;
302297
let D = 0;
303-
let MemriOp = 0;
304298
}
305299

306300
class DForm_4_fixedreg_zero<bits<6> opcode, bits<5> R, dag OOL, dag IOL,
@@ -378,7 +372,7 @@ class DForm_6_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr,
378372
// 1.7.5 DS-Form
379373
class DSForm_1<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr,
380374
InstrItinClass itin, list<dag> pattern>
381-
: I<opcode, OOL, IOL, asmstr, itin>, MemriOp {
375+
: I<opcode, OOL, IOL, asmstr, itin> {
382376
bits<5> RST;
383377
bits<5> RA;
384378
bits<14> D;
@@ -410,7 +404,7 @@ class DXForm<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
410404
// DQ-Form: [PO T RA DQ TX XO] or [PO S RA DQ SX XO]
411405
class DQ_RD6_RS5_DQ12<bits<6> opcode, bits<3> xo, dag OOL, dag IOL,
412406
string asmstr, InstrItinClass itin, list<dag> pattern>
413-
: I<opcode, OOL, IOL, asmstr, itin>, MemriOp {
407+
: I<opcode, OOL, IOL, asmstr, itin> {
414408
bits<6> XT;
415409
bits<5> RA;
416410
bits<12> DQ;
@@ -427,7 +421,7 @@ class DQ_RD6_RS5_DQ12<bits<6> opcode, bits<3> xo, dag OOL, dag IOL,
427421
class DQForm_RTp5_RA17_MEM<bits<6> opcode, bits<4> xo, dag OOL, dag IOL,
428422
string asmstr, InstrItinClass itin,
429423
list<dag> pattern>
430-
: I<opcode, OOL, IOL, asmstr, itin>, MemriOp {
424+
: I<opcode, OOL, IOL, asmstr, itin> {
431425
bits<5> RTp;
432426
bits<5> RA;
433427
bits<12> DQ;
@@ -1252,7 +1246,7 @@ class XX2_RD6_DCMX7_RS6<bits<6> opcode, bits<4> xo1, bits<3> xo2,
12521246

12531247
class XForm_XD6_RA5_RB5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
12541248
string asmstr, InstrItinClass itin, list<dag> pattern>
1255-
: I<opcode, OOL, IOL, asmstr, itin>, MemriOp {
1249+
: I<opcode, OOL, IOL, asmstr, itin> {
12561250
bits<5> RA;
12571251
bits<6> D;
12581252
bits<5> RB;

‎llvm/lib/Target/PowerPC/PPCInstrInfo.h

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -286,9 +286,6 @@ class PPCInstrInfo : public PPCGenInstrInfo {
286286
bool isZExt32To64(unsigned Opcode) const {
287287
return get(Opcode).TSFlags & PPCII::ZExt32To64;
288288
}
289-
bool isMemriOp(unsigned Opcode) const {
290-
return get(Opcode).TSFlags & PPCII::MemriOp;
291-
}
292289

293290
static bool isSameClassPhysRegCopy(unsigned Opcode) {
294291
unsigned CopyOpcodes[] = {PPC::OR, PPC::OR8, PPC::FMR,

‎llvm/lib/Target/PowerPC/PPCInstrInfo.td

Lines changed: 2 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -2303,7 +2303,7 @@ let isCodeGenOnly = 1 in
23032303
def LA : DForm_2<14, (outs gprc:$RST), (ins gprc_nor0:$RA, s16imm:$D),
23042304
"la $RST, $D($RA)", IIC_IntGeneral,
23052305
[(set i32:$RST, (add i32:$RA,
2306-
(PPClo tglobaladdr:$D, 0)))]>, MemriOp;
2306+
(PPClo tglobaladdr:$D, 0)))]>;
23072307
def MULLI : DForm_2< 7, (outs gprc:$RST), (ins gprc:$RA, s16imm:$D),
23082308
"mulli $RST, $RA, $D", IIC_IntMulLI,
23092309
[(set i32:$RST, (mul i32:$RA, imm32SExt16:$D))]>;
@@ -3466,10 +3466,6 @@ class PPCAsmPseudo<string asm, dag iops>
34663466
let isAsmParserOnly = 1;
34673467
let isPseudo = 1;
34683468
let hasNoSchedulingInfo = 1;
3469-
3470-
// Indicate that this instruction takes a register+immediate memory operand.
3471-
bits<1> MemriOp = 0;
3472-
let TSFlags{10} = MemriOp;
34733469
}
34743470

34753471
// Prefixed instructions may require access to the above defs at a later
@@ -4718,7 +4714,7 @@ def : InstAlias<"tlbilxva $RA, $RB", (TLBILX 3, gprc:$RA, gprc:$RB)>,
47184714
Requires<[IsBookE]>;
47194715
def : InstAlias<"tlbilxva $RB", (TLBILX 3, R0, gprc:$RB)>, Requires<[IsBookE]>;
47204716

4721-
def LAx : PPCAsmPseudo<"la $rA, $addr", (ins gprc:$rA, memri:$addr)>, MemriOp;
4717+
def LAx : PPCAsmPseudo<"la $rA, $addr", (ins gprc:$rA, memri:$addr)>;
47224718

47234719
def SUBI : PPCAsmPseudo<"subi $rA, $rB, $imm",
47244720
(ins gprc:$rA, gprc:$rB, s16imm:$imm)>;

‎llvm/lib/Target/PowerPC/PPCInstrP10.td

Lines changed: 11 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -138,10 +138,6 @@ class PI<bits<6> pref, bits<6> opcode, dag OOL, dag IOL, string asmstr,
138138
bits<1> Prefixed = 1; // This is a prefixed instruction.
139139
let TSFlags{7} = Prefixed;
140140

141-
// Indicate that this instruction takes a register+immediate memory operand.
142-
bits<1> MemriOp = 0;
143-
let TSFlags{10} = MemriOp;
144-
145141
// For cases where multiple instruction definitions really represent the
146142
// same underlying instruction but with one definition for 64-bit arguments
147143
// and one for 32-bit arguments, this bit breaks the degeneracy between
@@ -187,7 +183,7 @@ multiclass VXForm_VTB5_RCr<bits<10> xo, bits<5> R, dag OOL, dag IOL,
187183

188184
class MLS_DForm_R_SI34_RTA5_MEM<bits<6> opcode, dag OOL, dag IOL, string asmstr,
189185
InstrItinClass itin, list<dag> pattern>
190-
: PI<1, opcode, OOL, IOL, asmstr, itin>, MemriOp {
186+
: PI<1, opcode, OOL, IOL, asmstr, itin> {
191187
bits<5> RST;
192188
bits<5> RA;
193189
bits<34> D;
@@ -261,7 +257,7 @@ multiclass MLS_DForm_R_SI34_RTA5_p<bits<6> opcode, dag OOL, dag IOL,
261257

262258
class 8LS_DForm_R_SI34_RTA5_MEM<bits<6> opcode, dag OOL, dag IOL, string asmstr,
263259
InstrItinClass itin, list<dag> pattern>
264-
: PI<1, opcode, OOL, IOL, asmstr, itin>, MemriOp {
260+
: PI<1, opcode, OOL, IOL, asmstr, itin> {
265261
bits<5> RST;
266262
bits<5> RA;
267263
bits<34> D;
@@ -285,7 +281,7 @@ class 8LS_DForm_R_SI34_RTA5_MEM<bits<6> opcode, dag OOL, dag IOL, string asmstr,
285281
class 8LS_DForm_R_SI34_XT6_RA5_MEM<bits<5> opcode, dag OOL, dag IOL,
286282
string asmstr, InstrItinClass itin,
287283
list<dag> pattern>
288-
: PI<1, { opcode, ? }, OOL, IOL, asmstr, itin>, MemriOp {
284+
: PI<1, { opcode, ? }, OOL, IOL, asmstr, itin> {
289285
bits<6> XST;
290286
bits<5> RA;
291287
bits<34> D;
@@ -589,7 +585,7 @@ multiclass MLS_DForm_R_SI34_RTA5_MEM_p<bits<6> opcode, dag OOL, dag IOL,
589585
isPCRel;
590586
let isAsmParserOnly = 1, hasNoSchedulingInfo = 1 in {
591587
def nopc : MLS_DForm_R_SI34_RTA5_MEM<opcode, OOL, IOL, asmstr, itin, []>;
592-
let RA = 0, MemriOp = 0 in
588+
let RA = 0 in
593589
def onlypc : MLS_DForm_R_SI34_RTA5_MEM<opcode, OOL, PCRelOnly_IOL,
594590
asmstr_pcext, itin, []>, isPCRel;
595591
}
@@ -606,7 +602,7 @@ multiclass 8LS_DForm_R_SI34_RTA5_MEM_p<bits<6> opcode, dag OOL, dag IOL,
606602
isPCRel;
607603
let isAsmParserOnly = 1, hasNoSchedulingInfo = 1 in {
608604
def nopc : 8LS_DForm_R_SI34_RTA5_MEM<opcode, OOL, IOL, asmstr, itin, []>;
609-
let RA = 0, MemriOp = 0 in
605+
let RA = 0 in
610606
def onlypc : 8LS_DForm_R_SI34_RTA5_MEM<opcode, OOL, PCRelOnly_IOL,
611607
asmstr_pcext, itin, []>, isPCRel;
612608
}
@@ -623,7 +619,7 @@ multiclass 8LS_DForm_R_SI34_XT6_RA5_MEM_p<bits<5> opcode, dag OOL, dag IOL,
623619
isPCRel;
624620
let isAsmParserOnly = 1, hasNoSchedulingInfo = 1 in {
625621
def nopc : 8LS_DForm_R_SI34_XT6_RA5_MEM<opcode, OOL, IOL, asmstr, itin, []>;
626-
let RA = 0, MemriOp = 0 in
622+
let RA = 0 in
627623
def onlypc : 8LS_DForm_R_SI34_XT6_RA5_MEM<opcode, OOL, PCRelOnly_IOL,
628624
asmstr_pcext, itin, []>, isPCRel;
629625
}
@@ -851,7 +847,7 @@ let Predicates = [PrefixInstrs, HasP10Vector] in {
851847

852848
class DQForm_XTp5_RA17_MEM<bits<6> opcode, bits<4> xo, dag OOL, dag IOL,
853849
string asmstr, InstrItinClass itin, list<dag> pattern>
854-
: I<opcode, OOL, IOL, asmstr, itin>, MemriOp {
850+
: I<opcode, OOL, IOL, asmstr, itin> {
855851
bits<5> XTp;
856852
bits<5> RA;
857853
bits<12> DQ;
@@ -883,7 +879,7 @@ class XForm_XTp5_XAB5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
883879

884880
class 8LS_DForm_R_XTp5_SI34_MEM<bits<6> opcode, dag OOL, dag IOL, string asmstr,
885881
InstrItinClass itin, list<dag> pattern>
886-
: PI<1, opcode, OOL, IOL, asmstr, itin>, MemriOp {
882+
: PI<1, opcode, OOL, IOL, asmstr, itin> {
887883
bits<5> XTp;
888884
bits<5> RA;
889885
bits<34> D;
@@ -914,7 +910,7 @@ multiclass 8LS_DForm_R_XTp5_SI34_MEM_p<bits<6> opcode, dag OOL,
914910
isPCRel;
915911
let isAsmParserOnly = 1, hasNoSchedulingInfo = 1 in {
916912
def nopc : 8LS_DForm_R_XTp5_SI34_MEM<opcode, OOL, IOL, asmstr, itin, []>;
917-
let RA = 0, MemriOp = 0 in
913+
let RA = 0 in
918914
def onlypc : 8LS_DForm_R_XTp5_SI34_MEM<opcode, OOL, PCRelOnly_IOL,
919915
asmstr_pcext, itin, []>, isPCRel;
920916
}
@@ -2510,7 +2506,7 @@ let Predicates = [IsISA3_1, PrefixInstrs], isAsmParserOnly = 1, hasNoSchedulingI
25102506
let Interpretation64Bit = 1 in {
25112507
def PLA8 : MLS_DForm_SI34_RT5<14, (outs g8rc:$RT),
25122508
(ins g8rc_nox0:$RA, s34imm:$SI),
2513-
"pla $RT, ${SI} ${RA}", IIC_IntSimple, []>, MemriOp;
2509+
"pla $RT, ${SI} ${RA}", IIC_IntSimple, []>;
25142510
def PLA8pc : MLS_DForm_SI34_RT5<14, (outs g8rc:$RT),
25152511
(ins s34imm_pcrel:$SI),
25162512
"pla $RT, $SI", IIC_IntSimple, []>, isPCRel;
@@ -2521,7 +2517,7 @@ let Predicates = [IsISA3_1, PrefixInstrs], isAsmParserOnly = 1, hasNoSchedulingI
25212517

25222518
def PLA : MLS_DForm_SI34_RT5<14, (outs gprc:$RT),
25232519
(ins gprc_nor0:$RA, s34imm:$SI),
2524-
"pla $RT, ${SI} ${RA}", IIC_IntSimple, []>, MemriOp;
2520+
"pla $RT, ${SI} ${RA}", IIC_IntSimple, []>;
25252521
def PLApc : MLS_DForm_SI34_RT5<14, (outs gprc:$RT),
25262522
(ins s34imm_pcrel:$SI),
25272523
"pla $RT, $SI", IIC_IntSimple, []>, isPCRel;

‎llvm/lib/Target/PowerPC/PPCInstrSPE.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -114,7 +114,7 @@ class EVXForm_4<bits<8> xo, dag OOL, dag IOL, string asmstr,
114114

115115
class EVXForm_D<bits<11> xo, dag OOL, dag IOL, string asmstr,
116116
InstrItinClass itin, list<dag> pattern> :
117-
I<4, OOL, IOL, asmstr, itin>, MemriOp {
117+
I<4, OOL, IOL, asmstr, itin> {
118118
bits<5> RT;
119119
bits<5> RA;
120120
bits<5> D;

‎llvm/test/CodeGen/PowerPC/2007-01-31-InlineAsmAddrMode.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -11,7 +11,7 @@ define void @test1() {
1111
entry:
1212
%Out = alloca %struct.A, align 4 ; <ptr> [#uses=1]
1313
%tmp2 = getelementptr %struct.A, ptr %Out, i32 0, i32 1
14-
%tmp5 = call i32 asm "lbz $0, $1", "=r,m"(ptr %tmp2 )
14+
%tmp5 = call i32 asm "lwbrx $0, $1", "=r,m"(ptr %tmp2 )
1515
ret void
1616
}
1717

‎llvm/test/CodeGen/PowerPC/2009-07-16-InlineAsm-M-Operand.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -10,7 +10,7 @@ define void @memory_asm_operand(i32 %a) {
1010
; "m" operand will be represented as:
1111
; INLINEASM fake $0, 10, %R2, 20, -4, %R1
1212
; It is difficult to find the flag operand (20) when starting from %R1
13-
call i32 asm "lbz $0, $1", "=r,m" (i32 %a)
13+
call i32 asm "lbzx $0, $1", "=r,m" (i32 %a)
1414
ret void
1515
}
1616

‎llvm/test/MC/PowerPC/ppc64-errors.s

Lines changed: 0 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -143,18 +143,3 @@
143143
# CHECK: error: invalid operand for instruction
144144
# CHECK-NEXT: lwarx 1, 2, 3, a
145145
lwarx 1, 2, 3, a
146-
147-
# Instruction requires memory operand
148-
# CHECK: error: invalid operand for instruction
149-
# CHECK-NEXT: la 3, 3, 10
150-
la 3, 3, 10
151-
152-
# Instruction doesn't support memory operands
153-
# CHECK: error: invalid operand for instruction
154-
# CHECK-NEXT: addi 3, 10(3)
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addi 3, 10(3)
156-
157-
# Invalid memory operand position
158-
# CHECK: error: invalid operand for instruction
159-
# CHECK-NEXT: la 0(3), 3
160-
la 0(3), 3

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