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alexey-bataevalexey-bataev
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[SLP]Cost for a constant buildvector.
In many cases constant buildvector results in a vector load from a constant/data pool. Need to consider this cost too. Differential Revision: https://reviews.llvm.org/D126885
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6 files changed

+88
-58
lines changed

6 files changed

+88
-58
lines changed

‎llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp

Lines changed: 13 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -440,8 +440,19 @@ InstructionCost RISCVTTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src,
440440
TTI::TargetCostKind CostKind,
441441
TTI::OperandValueKind OpdInfo,
442442
const Instruction *I) {
443-
return BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, CostKind,
444-
OpdInfo, I);
443+
InstructionCost Cost = 0;
444+
if (Opcode == Instruction::Store && isa<VectorType>(Src) &&
445+
(OpdInfo == TTI::OK_UniformConstantValue ||
446+
OpdInfo == TTI::OK_NonUniformConstantValue)) {
447+
APInt PseudoAddr = APInt::getAllOnes(DL.getPointerSizeInBits());
448+
// Add a cost of address load + the cost of the vector load.
449+
Cost += RISCVMatInt::getIntMatCost(PseudoAddr, DL.getPointerSizeInBits(),
450+
getST()->getFeatureBits()) +
451+
getMemoryOpCost(Instruction::Load, Src, DL.getABITypeAlign(Src),
452+
/*AddressSpace=*/0, CostKind);
453+
}
454+
return Cost + BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace,
455+
CostKind, OpdInfo, I);
445456
}
446457

447458
void RISCVTTIImpl::getUnrollingPreferences(Loop *L, ScalarEvolution &SE,

‎llvm/lib/Target/X86/X86TargetTransformInfo.cpp

Lines changed: 14 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1079,7 +1079,8 @@ InstructionCost X86TTIImpl::getArithmeticInstrCost(
10791079
}
10801080

10811081
// Fallback to the default implementation.
1082-
return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info, Op2Info);
1082+
return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info, Op2Info,
1083+
Opd1PropInfo, Opd2PropInfo, Args, CxtI);
10831084
}
10841085

10851086
InstructionCost X86TTIImpl::getShuffleCost(TTI::ShuffleKind Kind,
@@ -4077,20 +4078,28 @@ InstructionCost X86TTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src,
40774078

40784079
auto *VTy = dyn_cast<FixedVectorType>(Src);
40794080

4081+
InstructionCost Cost = 0;
4082+
4083+
// Add a cost for constant load to vector.
4084+
if (Opcode == Instruction::Store &&
4085+
(OpdInfo == TTI::OK_UniformConstantValue ||
4086+
OpdInfo == TTI::OK_NonUniformConstantValue))
4087+
Cost += getMemoryOpCost(Instruction::Load, Src, DL.getABITypeAlign(Src),
4088+
/*AddressSpace=*/0, CostKind);
4089+
40804090
// Handle the simple case of non-vectors.
40814091
// NOTE: this assumes that legalization never creates vector from scalars!
4082-
if (!VTy || !LT.second.isVector())
4092+
if (!VTy || !LT.second.isVector()) {
40834093
// Each load/store unit costs 1.
4084-
return LT.first * 1;
4094+
return (LT.second.isFloatingPoint() ? Cost : 0) + LT.first * 1;
4095+
}
40854096

40864097
bool IsLoad = Opcode == Instruction::Load;
40874098

40884099
Type *EltTy = VTy->getElementType();
40894100

40904101
const int EltTyBits = DL.getTypeSizeInBits(EltTy);
40914102

4092-
InstructionCost Cost = 0;
4093-
40944103
// Source of truth: how many elements were there in the original IR vector?
40954104
const unsigned SrcNumElt = VTy->getNumElements();
40964105

‎llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -6414,6 +6414,12 @@ InstructionCost BoUpSLP::getEntryCost(const TreeEntry *E,
64146414
CommonCost -= (EntryVF - VL.size()) * ScalarEltCost;
64156415
}
64166416
InstructionCost ScalarCost = VecTy->getNumElements() * ScalarEltCost;
6417+
for (unsigned I = 0, Num = VL0->getNumOperands(); I < Num; ++I) {
6418+
if (all_of(VL, [I](Value *V) {
6419+
return isConstant(cast<Instruction>(V)->getOperand(I));
6420+
}))
6421+
Operands[I] = ConstantVector::getNullValue(VecTy);
6422+
}
64176423
InstructionCost VecCost =
64186424
TTI->getArithmeticInstrCost(E->getOpcode(), VecTy, CostKind, Op1VK,
64196425
Op2VK, Op1VP, Op2VP, Operands, VL0);

‎llvm/test/Analysis/CostModel/X86/arith-fp.ll

Lines changed: 39 additions & 39 deletions
Original file line numberDiff line numberDiff line change
@@ -626,9 +626,9 @@ define i32 @fdiv(i32 %arg) {
626626
define i32 @frem(i32 %arg) {
627627
; SSE1-LABEL: 'frem'
628628
; SSE1-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %F32 = frem float undef, undef
629-
; SSE1-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %V4F32 = frem <4 x float> undef, undef
630-
; SSE1-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %V8F32 = frem <8 x float> undef, undef
631-
; SSE1-NEXT: Cost Model: Found an estimated cost of 56 for instruction: %V16F32 = frem <16 x float> undef, undef
629+
; SSE1-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V4F32 = frem <4 x float> undef, undef
630+
; SSE1-NEXT: Cost Model: Found an estimated cost of 22 for instruction: %V8F32 = frem <8 x float> undef, undef
631+
; SSE1-NEXT: Cost Model: Found an estimated cost of 44 for instruction: %V16F32 = frem <16 x float> undef, undef
632632
; SSE1-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %F64 = frem double undef, undef
633633
; SSE1-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2F64 = frem <2 x double> undef, undef
634634
; SSE1-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V4F64 = frem <4 x double> undef, undef
@@ -637,68 +637,68 @@ define i32 @frem(i32 %arg) {
637637
;
638638
; SSE2-LABEL: 'frem'
639639
; SSE2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %F32 = frem float undef, undef
640-
; SSE2-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %V4F32 = frem <4 x float> undef, undef
641-
; SSE2-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %V8F32 = frem <8 x float> undef, undef
642-
; SSE2-NEXT: Cost Model: Found an estimated cost of 56 for instruction: %V16F32 = frem <16 x float> undef, undef
640+
; SSE2-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V4F32 = frem <4 x float> undef, undef
641+
; SSE2-NEXT: Cost Model: Found an estimated cost of 22 for instruction: %V8F32 = frem <8 x float> undef, undef
642+
; SSE2-NEXT: Cost Model: Found an estimated cost of 44 for instruction: %V16F32 = frem <16 x float> undef, undef
643643
; SSE2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %F64 = frem double undef, undef
644-
; SSE2-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V2F64 = frem <2 x double> undef, undef
645-
; SSE2-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V4F64 = frem <4 x double> undef, undef
646-
; SSE2-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %V8F64 = frem <8 x double> undef, undef
644+
; SSE2-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V2F64 = frem <2 x double> undef, undef
645+
; SSE2-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V4F64 = frem <4 x double> undef, undef
646+
; SSE2-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %V8F64 = frem <8 x double> undef, undef
647647
; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
648648
;
649649
; SSE42-LABEL: 'frem'
650650
; SSE42-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %F32 = frem float undef, undef
651-
; SSE42-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %V4F32 = frem <4 x float> undef, undef
652-
; SSE42-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %V8F32 = frem <8 x float> undef, undef
653-
; SSE42-NEXT: Cost Model: Found an estimated cost of 56 for instruction: %V16F32 = frem <16 x float> undef, undef
651+
; SSE42-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V4F32 = frem <4 x float> undef, undef
652+
; SSE42-NEXT: Cost Model: Found an estimated cost of 22 for instruction: %V8F32 = frem <8 x float> undef, undef
653+
; SSE42-NEXT: Cost Model: Found an estimated cost of 44 for instruction: %V16F32 = frem <16 x float> undef, undef
654654
; SSE42-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %F64 = frem double undef, undef
655-
; SSE42-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V2F64 = frem <2 x double> undef, undef
656-
; SSE42-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V4F64 = frem <4 x double> undef, undef
657-
; SSE42-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %V8F64 = frem <8 x double> undef, undef
655+
; SSE42-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V2F64 = frem <2 x double> undef, undef
656+
; SSE42-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V4F64 = frem <4 x double> undef, undef
657+
; SSE42-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %V8F64 = frem <8 x double> undef, undef
658658
; SSE42-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
659659
;
660660
; AVX-LABEL: 'frem'
661661
; AVX-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %F32 = frem float undef, undef
662-
; AVX-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %V4F32 = frem <4 x float> undef, undef
663-
; AVX-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %V8F32 = frem <8 x float> undef, undef
664-
; AVX-NEXT: Cost Model: Found an estimated cost of 62 for instruction: %V16F32 = frem <16 x float> undef, undef
662+
; AVX-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V4F32 = frem <4 x float> undef, undef
663+
; AVX-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %V8F32 = frem <8 x float> undef, undef
664+
; AVX-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %V16F32 = frem <16 x float> undef, undef
665665
; AVX-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %F64 = frem double undef, undef
666-
; AVX-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V2F64 = frem <2 x double> undef, undef
667-
; AVX-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %V4F64 = frem <4 x double> undef, undef
668-
; AVX-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %V8F64 = frem <8 x double> undef, undef
666+
; AVX-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V2F64 = frem <2 x double> undef, undef
667+
; AVX-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V4F64 = frem <4 x double> undef, undef
668+
; AVX-NEXT: Cost Model: Found an estimated cost of 22 for instruction: %V8F64 = frem <8 x double> undef, undef
669669
; AVX-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
670670
;
671671
; AVX512-LABEL: 'frem'
672672
; AVX512-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %F32 = frem float undef, undef
673-
; AVX512-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %V4F32 = frem <4 x float> undef, undef
674-
; AVX512-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %V8F32 = frem <8 x float> undef, undef
675-
; AVX512-NEXT: Cost Model: Found an estimated cost of 63 for instruction: %V16F32 = frem <16 x float> undef, undef
673+
; AVX512-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V4F32 = frem <4 x float> undef, undef
674+
; AVX512-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %V8F32 = frem <8 x float> undef, undef
675+
; AVX512-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %V16F32 = frem <16 x float> undef, undef
676676
; AVX512-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %F64 = frem double undef, undef
677-
; AVX512-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V2F64 = frem <2 x double> undef, undef
678-
; AVX512-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %V4F64 = frem <4 x double> undef, undef
679-
; AVX512-NEXT: Cost Model: Found an estimated cost of 30 for instruction: %V8F64 = frem <8 x double> undef, undef
677+
; AVX512-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V2F64 = frem <2 x double> undef, undef
678+
; AVX512-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V4F64 = frem <4 x double> undef, undef
679+
; AVX512-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %V8F64 = frem <8 x double> undef, undef
680680
; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
681681
;
682682
; SLM-LABEL: 'frem'
683683
; SLM-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %F32 = frem float undef, undef
684-
; SLM-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %V4F32 = frem <4 x float> undef, undef
685-
; SLM-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %V8F32 = frem <8 x float> undef, undef
686-
; SLM-NEXT: Cost Model: Found an estimated cost of 56 for instruction: %V16F32 = frem <16 x float> undef, undef
684+
; SLM-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V4F32 = frem <4 x float> undef, undef
685+
; SLM-NEXT: Cost Model: Found an estimated cost of 22 for instruction: %V8F32 = frem <8 x float> undef, undef
686+
; SLM-NEXT: Cost Model: Found an estimated cost of 44 for instruction: %V16F32 = frem <16 x float> undef, undef
687687
; SLM-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %F64 = frem double undef, undef
688-
; SLM-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V2F64 = frem <2 x double> undef, undef
689-
; SLM-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V4F64 = frem <4 x double> undef, undef
690-
; SLM-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %V8F64 = frem <8 x double> undef, undef
688+
; SLM-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V2F64 = frem <2 x double> undef, undef
689+
; SLM-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V4F64 = frem <4 x double> undef, undef
690+
; SLM-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %V8F64 = frem <8 x double> undef, undef
691691
; SLM-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
692692
;
693693
; GLM-LABEL: 'frem'
694694
; GLM-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %F32 = frem float undef, undef
695-
; GLM-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %V4F32 = frem <4 x float> undef, undef
696-
; GLM-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %V8F32 = frem <8 x float> undef, undef
697-
; GLM-NEXT: Cost Model: Found an estimated cost of 56 for instruction: %V16F32 = frem <16 x float> undef, undef
695+
; GLM-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V4F32 = frem <4 x float> undef, undef
696+
; GLM-NEXT: Cost Model: Found an estimated cost of 22 for instruction: %V8F32 = frem <8 x float> undef, undef
697+
; GLM-NEXT: Cost Model: Found an estimated cost of 44 for instruction: %V16F32 = frem <16 x float> undef, undef
698698
; GLM-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %F64 = frem double undef, undef
699-
; GLM-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V2F64 = frem <2 x double> undef, undef
700-
; GLM-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V4F64 = frem <4 x double> undef, undef
701-
; GLM-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %V8F64 = frem <8 x double> undef, undef
699+
; GLM-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V2F64 = frem <2 x double> undef, undef
700+
; GLM-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V4F64 = frem <4 x double> undef, undef
701+
; GLM-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %V8F64 = frem <8 x double> undef, undef
702702
; GLM-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
703703
;
704704
%F32 = frem float undef, undef

‎llvm/test/Transforms/SLPVectorizer/RISCV/rvv-min-vector-size.ll

Lines changed: 9 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -12,11 +12,13 @@ target triple = "riscv64"
1212
define void @foo(i64* nocapture writeonly %da) {
1313
; CHECK-128-LABEL: @foo(
1414
; CHECK-128-NEXT: entry:
15-
; CHECK-128-NEXT: [[TMP0:%.*]] = bitcast i64* [[DA:%.*]] to <2 x i64>*
16-
; CHECK-128-NEXT: store <2 x i64> <i64 0, i64 1>, <2 x i64>* [[TMP0]], align 8
15+
; CHECK-128-NEXT: store i64 0, i64* [[DA:%.*]], align 8
16+
; CHECK-128-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i64, i64* [[DA]], i64 1
17+
; CHECK-128-NEXT: store i64 1, i64* [[ARRAYIDX1]], align 8
1718
; CHECK-128-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i64, i64* [[DA]], i64 2
18-
; CHECK-128-NEXT: [[TMP1:%.*]] = bitcast i64* [[ARRAYIDX2]] to <2 x i64>*
19-
; CHECK-128-NEXT: store <2 x i64> <i64 2, i64 3>, <2 x i64>* [[TMP1]], align 8
19+
; CHECK-128-NEXT: store i64 2, i64* [[ARRAYIDX2]], align 8
20+
; CHECK-128-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds i64, i64* [[DA]], i64 3
21+
; CHECK-128-NEXT: store i64 3, i64* [[ARRAYIDX3]], align 8
2022
; CHECK-128-NEXT: ret void
2123
;
2224
; CHECK-256-LABEL: @foo(
@@ -45,8 +47,9 @@ entry:
4547
define void @foo8(i8* nocapture writeonly %da) {
4648
; CHECK-LABEL: @foo8(
4749
; CHECK-NEXT: entry:
48-
; CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[DA:%.*]] to <2 x i8>*
49-
; CHECK-NEXT: store <2 x i8> <i8 0, i8 1>, <2 x i8>* [[TMP0]], align 8
50+
; CHECK-NEXT: store i8 0, i8* [[DA:%.*]], align 8
51+
; CHECK-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i8, i8* [[DA]], i8 1
52+
; CHECK-NEXT: store i8 1, i8* [[ARRAYIDX1]], align 8
5053
; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i8, i8* [[DA]], i8 2
5154
; CHECK-NEXT: ret void
5255
;

‎llvm/test/Transforms/SLPVectorizer/X86/crash_bullet.ll

Lines changed: 7 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -14,18 +14,19 @@ define void @_ZN23btGeneric6DofConstraint8getInfo1EPN17btTypedConstraint17btCons
1414
; CHECK-NEXT: ret void
1515
; CHECK: if.else:
1616
; CHECK-NEXT: [[M_NUMCONSTRAINTROWS4:%.*]] = getelementptr inbounds %"struct.btTypedConstraint::btConstraintInfo1.17.157.357.417.477.960", %"struct.btTypedConstraint::btConstraintInfo1.17.157.357.417.477.960"* [[INFO:%.*]], i64 0, i32 0
17+
; CHECK-NEXT: [[NUB5:%.*]] = getelementptr inbounds %"struct.btTypedConstraint::btConstraintInfo1.17.157.357.417.477.960", %"struct.btTypedConstraint::btConstraintInfo1.17.157.357.417.477.960"* [[INFO]], i64 0, i32 1
1718
; CHECK-NEXT: br i1 undef, label [[LAND_LHS_TRUE_I_1:%.*]], label [[IF_THEN7_1:%.*]]
1819
; CHECK: land.lhs.true.i.1:
1920
; CHECK-NEXT: br i1 undef, label [[FOR_INC_1:%.*]], label [[IF_THEN7_1]]
2021
; CHECK: if.then7.1:
21-
; CHECK-NEXT: [[TMP0:%.*]] = bitcast i32* [[M_NUMCONSTRAINTROWS4]] to <2 x i32>*
22-
; CHECK-NEXT: store <2 x i32> <i32 1, i32 5>, <2 x i32>* [[TMP0]], align 4
22+
; CHECK-NEXT: store i32 1, i32* [[M_NUMCONSTRAINTROWS4]], align 4
23+
; CHECK-NEXT: store i32 5, i32* [[NUB5]], align 4
2324
; CHECK-NEXT: br label [[FOR_INC_1]]
2425
; CHECK: for.inc.1:
25-
; CHECK-NEXT: [[TMP1:%.*]] = phi <2 x i32> [ <i32 1, i32 5>, [[IF_THEN7_1]] ], [ <i32 0, i32 6>, [[LAND_LHS_TRUE_I_1]] ]
26-
; CHECK-NEXT: [[TMP2:%.*]] = add nsw <2 x i32> [[TMP1]], <i32 1, i32 -1>
27-
; CHECK-NEXT: [[TMP3:%.*]] = bitcast i32* [[M_NUMCONSTRAINTROWS4]] to <2 x i32>*
28-
; CHECK-NEXT: store <2 x i32> [[TMP2]], <2 x i32>* [[TMP3]], align 4
26+
; CHECK-NEXT: [[TMP0:%.*]] = phi <2 x i32> [ <i32 1, i32 5>, [[IF_THEN7_1]] ], [ <i32 0, i32 6>, [[LAND_LHS_TRUE_I_1]] ]
27+
; CHECK-NEXT: [[TMP1:%.*]] = add nsw <2 x i32> [[TMP0]], <i32 1, i32 -1>
28+
; CHECK-NEXT: [[TMP2:%.*]] = bitcast i32* [[M_NUMCONSTRAINTROWS4]] to <2 x i32>*
29+
; CHECK-NEXT: store <2 x i32> [[TMP1]], <2 x i32>* [[TMP2]], align 4
2930
; CHECK-NEXT: unreachable
3031
;
3132
entry:

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