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; RUN: opt -S -passes=lowertypetests -mtriple=riscv32-unknown-linux-gnu %s | FileCheck --check-prefixes=RISCV,NATIVE %s
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; RUN: opt -S -passes=lowertypetests -mtriple=riscv64-unknown-linux-gnu %s | FileCheck --check-prefixes=RISCV,NATIVE %s
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; RUN: opt -S -passes=lowertypetests -mtriple=wasm32-unknown-unknown %s | FileCheck --check-prefix=WASM32 %s
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+ ; RUN: opt -S -passes=lowertypetests -mtriple=loongarch64-unknown-linux-gnu %s | FileCheck --check-prefixes=LOONGARCH64,NATIVE %s
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; The right format for Arm jump tables depends on the selected
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; subtarget, so we can't get these tests right without the Arm target
@@ -34,6 +35,7 @@ target datalayout = "e-p:64:64"
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; THUMB: @g = internal alias void (), getelementptr inbounds ([2 x [4 x i8]], ptr @[[JT]], i64 0, i64 1)
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; THUMBV6M: @g = internal alias void (), getelementptr inbounds ([2 x [16 x i8]], ptr @[[JT]], i64 0, i64 1)
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; RISCV: @g = internal alias void (), getelementptr inbounds ([2 x [8 x i8]], ptr @[[JT]], i64 0, i64 1)
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+ ; LOONGARCH64: @g = internal alias void (), getelementptr inbounds ([2 x [8 x i8]], ptr @[[JT]], i64 0, i64 1)
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; NATIVE: define hidden void @f.cfi()
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; WASM32: define void @f() !type !{{[0-9]+}} !wasm.index ![[I0:[0-9]+]]
@@ -65,6 +67,7 @@ define i1 @foo(ptr %p) {
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; THUMB: define private void @[[JT]]() #[[ATTR:.*]] align 4 {
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; THUMBV6M: define private void @[[JT]]() #[[ATTR:.*]] align 16 {
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; RISCV: define private void @[[JT]]() #[[ATTR:.*]] align 8 {
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+ ; LOONGARCH64: define private void @[[JT]]() #[[ATTR:.*]] align 8 {
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; X86: jmp ${0:c}@plt
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; X86-SAME: int3
@@ -99,6 +102,11 @@ define i1 @foo(ptr %p) {
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; RISCV: tail $0@plt
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; RISCV-SAME: tail $1@plt
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+ ; LOONGARCH64: pcalau12i $$t0, %pc_hi20($0)
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+ ; LOONGARCH64-SAME: jirl $$r0, $$t0, %pc_lo12($0)
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+ ; LOONGARCH64-SAME: pcalau12i $$t0, %pc_hi20($1)
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+ ; LOONGARCH64-SAME: jirl $$r0, $$t0, %pc_lo12($1)
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+
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; NATIVE-SAME: "s,s"(ptr @f.cfi, ptr @g.cfi)
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; X86-LINUX: attributes #[[ATTR]] = { naked nocf_check nounwind }
@@ -107,6 +115,7 @@ define i1 @foo(ptr %p) {
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; THUMB: attributes #[[ATTR]] = { naked nounwind "branch-target-enforcement"="false" "sign-return-address"="none" "target-cpu"="cortex-a8" "target-features"="+thumb-mode" }
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; THUMBV6M: attributes #[[ATTR]] = { naked nounwind "branch-target-enforcement"="false" "sign-return-address"="none" "target-features"="+thumb-mode" }
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; RISCV: attributes #[[ATTR]] = { naked nounwind "target-features"="-c,-relax" }
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+ ; LOONGARCH64: attributes #[[ATTR]] = { naked nounwind }
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; WASM32: ![[I0]] = !{i64 1}
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; WASM32: ![[I1]] = !{i64 2}
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