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[RISCV] Move RISCVInsertVSETVLI after CSR/VXRM passes (#91701)
This further splits off #91440 to inch RISCVInsertVSETVLI closer to post vector regalloc. As noted in #91440, most of the diffs are from moving vsetvli insertion after the vxrm/csr insertion passes, but these are getting conflated with the changes from moving to LiveIntervals. One idea was that we could try and remove some of these diffs by manually moving back the vsetvlis past the vxrm/csr instructions. But this meant having to touch up the LiveIntervals again which seemed to lead to even more diffs. This instead just moves RISCVInsertVSETVLI after RISCVInsertReadWriteCSR and RISCVInsertWriteVXRM so we can isolate those changes.
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+4519
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lines changed

‎llvm/lib/Target/RISCV/RISCVTargetMachine.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -541,9 +541,9 @@ void RISCVPassConfig::addPreRegAlloc() {
541541
addPass(createRISCVPreRAExpandPseudoPass());
542542
if (TM->getOptLevel() != CodeGenOptLevel::None)
543543
addPass(createRISCVMergeBaseOffsetOptPass());
544-
addPass(createRISCVInsertVSETVLIPass());
545544
addPass(createRISCVInsertReadWriteCSRPass());
546545
addPass(createRISCVInsertWriteVXRMPass());
546+
addPass(createRISCVInsertVSETVLIPass());
547547
}
548548

549549
void RISCVPassConfig::addFastRegAlloc() {

‎llvm/test/CodeGen/RISCV/O0-pipeline.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -40,9 +40,9 @@
4040
; CHECK-NEXT: Finalize ISel and expand pseudo-instructions
4141
; CHECK-NEXT: Local Stack Slot Allocation
4242
; CHECK-NEXT: RISC-V Pre-RA pseudo instruction expansion pass
43-
; CHECK-NEXT: RISC-V Insert VSETVLI pass
4443
; CHECK-NEXT: RISC-V Insert Read/Write CSR Pass
4544
; CHECK-NEXT: RISC-V Insert Write VXRM Pass
45+
; CHECK-NEXT: RISC-V Insert VSETVLI pass
4646
; CHECK-NEXT: Init Undef Pass
4747
; CHECK-NEXT: Eliminate PHI nodes for register allocation
4848
; CHECK-NEXT: Two-Address instruction pass

‎llvm/test/CodeGen/RISCV/O3-pipeline.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -115,9 +115,9 @@
115115
; RV64-NEXT: RISC-V Optimize W Instructions
116116
; CHECK-NEXT: RISC-V Pre-RA pseudo instruction expansion pass
117117
; CHECK-NEXT: RISC-V Merge Base Offset
118-
; CHECK-NEXT: RISC-V Insert VSETVLI pass
119118
; CHECK-NEXT: RISC-V Insert Read/Write CSR Pass
120119
; CHECK-NEXT: RISC-V Insert Write VXRM Pass
120+
; CHECK-NEXT: RISC-V Insert VSETVLI pass
121121
; CHECK-NEXT: Detect Dead Lanes
122122
; CHECK-NEXT: Init Undef Pass
123123
; CHECK-NEXT: Process Implicit Definitions

‎llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll

Lines changed: 18 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -15,8 +15,8 @@ define <vscale x 1 x half> @vp_ceil_vv_nxv1f16(<vscale x 1 x half> %va, <vscale
1515
; CHECK-NEXT: vfabs.v v9, v8, v0.t
1616
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
1717
; CHECK-NEXT: vmflt.vf v0, v9, fa5, v0.t
18-
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
1918
; CHECK-NEXT: fsrmi a0, 3
19+
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
2020
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
2121
; CHECK-NEXT: fsrm a0
2222
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -57,8 +57,8 @@ define <vscale x 2 x half> @vp_ceil_vv_nxv2f16(<vscale x 2 x half> %va, <vscale
5757
; CHECK-NEXT: vfabs.v v9, v8, v0.t
5858
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
5959
; CHECK-NEXT: vmflt.vf v0, v9, fa5, v0.t
60-
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
6160
; CHECK-NEXT: fsrmi a0, 3
61+
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
6262
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
6363
; CHECK-NEXT: fsrm a0
6464
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -99,8 +99,8 @@ define <vscale x 4 x half> @vp_ceil_vv_nxv4f16(<vscale x 4 x half> %va, <vscale
9999
; CHECK-NEXT: vfabs.v v9, v8, v0.t
100100
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu
101101
; CHECK-NEXT: vmflt.vf v0, v9, fa5, v0.t
102-
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
103102
; CHECK-NEXT: fsrmi a0, 3
103+
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
104104
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
105105
; CHECK-NEXT: fsrm a0
106106
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -142,8 +142,8 @@ define <vscale x 8 x half> @vp_ceil_vv_nxv8f16(<vscale x 8 x half> %va, <vscale
142142
; CHECK-NEXT: vfabs.v v12, v8, v0.t
143143
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu
144144
; CHECK-NEXT: vmflt.vf v10, v12, fa5, v0.t
145-
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
146145
; CHECK-NEXT: fsrmi a0, 3
146+
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
147147
; CHECK-NEXT: vmv1r.v v0, v10
148148
; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t
149149
; CHECK-NEXT: fsrm a0
@@ -186,8 +186,8 @@ define <vscale x 16 x half> @vp_ceil_vv_nxv16f16(<vscale x 16 x half> %va, <vsca
186186
; CHECK-NEXT: vfabs.v v16, v8, v0.t
187187
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, mu
188188
; CHECK-NEXT: vmflt.vf v12, v16, fa5, v0.t
189-
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
190189
; CHECK-NEXT: fsrmi a0, 3
190+
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
191191
; CHECK-NEXT: vmv1r.v v0, v12
192192
; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t
193193
; CHECK-NEXT: fsrm a0
@@ -230,8 +230,8 @@ define <vscale x 32 x half> @vp_ceil_vv_nxv32f16(<vscale x 32 x half> %va, <vsca
230230
; CHECK-NEXT: vfabs.v v24, v8, v0.t
231231
; CHECK-NEXT: vsetvli zero, zero, e16, m8, ta, mu
232232
; CHECK-NEXT: vmflt.vf v16, v24, fa5, v0.t
233-
; CHECK-NEXT: vsetvli zero, zero, e16, m8, ta, ma
234233
; CHECK-NEXT: fsrmi a0, 3
234+
; CHECK-NEXT: vsetvli zero, zero, e16, m8, ta, ma
235235
; CHECK-NEXT: vmv1r.v v0, v16
236236
; CHECK-NEXT: vfcvt.x.f.v v24, v8, v0.t
237237
; CHECK-NEXT: fsrm a0
@@ -273,8 +273,8 @@ define <vscale x 1 x float> @vp_ceil_vv_nxv1f32(<vscale x 1 x float> %va, <vscal
273273
; CHECK-NEXT: fmv.w.x fa5, a0
274274
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
275275
; CHECK-NEXT: vmflt.vf v0, v9, fa5, v0.t
276-
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
277276
; CHECK-NEXT: fsrmi a0, 3
277+
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
278278
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
279279
; CHECK-NEXT: fsrm a0
280280
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -315,8 +315,8 @@ define <vscale x 2 x float> @vp_ceil_vv_nxv2f32(<vscale x 2 x float> %va, <vscal
315315
; CHECK-NEXT: fmv.w.x fa5, a0
316316
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
317317
; CHECK-NEXT: vmflt.vf v0, v9, fa5, v0.t
318-
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
319318
; CHECK-NEXT: fsrmi a0, 3
319+
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
320320
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
321321
; CHECK-NEXT: fsrm a0
322322
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -358,8 +358,8 @@ define <vscale x 4 x float> @vp_ceil_vv_nxv4f32(<vscale x 4 x float> %va, <vscal
358358
; CHECK-NEXT: fmv.w.x fa5, a0
359359
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu
360360
; CHECK-NEXT: vmflt.vf v10, v12, fa5, v0.t
361-
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
362361
; CHECK-NEXT: fsrmi a0, 3
362+
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
363363
; CHECK-NEXT: vmv1r.v v0, v10
364364
; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t
365365
; CHECK-NEXT: fsrm a0
@@ -402,8 +402,8 @@ define <vscale x 8 x float> @vp_ceil_vv_nxv8f32(<vscale x 8 x float> %va, <vscal
402402
; CHECK-NEXT: fmv.w.x fa5, a0
403403
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu
404404
; CHECK-NEXT: vmflt.vf v12, v16, fa5, v0.t
405-
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
406405
; CHECK-NEXT: fsrmi a0, 3
406+
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
407407
; CHECK-NEXT: vmv1r.v v0, v12
408408
; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t
409409
; CHECK-NEXT: fsrm a0
@@ -446,8 +446,8 @@ define <vscale x 16 x float> @vp_ceil_vv_nxv16f32(<vscale x 16 x float> %va, <vs
446446
; CHECK-NEXT: fmv.w.x fa5, a0
447447
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu
448448
; CHECK-NEXT: vmflt.vf v16, v24, fa5, v0.t
449-
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
450449
; CHECK-NEXT: fsrmi a0, 3
450+
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
451451
; CHECK-NEXT: vmv1r.v v0, v16
452452
; CHECK-NEXT: vfcvt.x.f.v v24, v8, v0.t
453453
; CHECK-NEXT: fsrm a0
@@ -489,8 +489,8 @@ define <vscale x 1 x double> @vp_ceil_vv_nxv1f64(<vscale x 1 x double> %va, <vsc
489489
; CHECK-NEXT: vfabs.v v9, v8, v0.t
490490
; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, mu
491491
; CHECK-NEXT: vmflt.vf v0, v9, fa5, v0.t
492-
; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma
493492
; CHECK-NEXT: fsrmi a0, 3
493+
; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma
494494
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
495495
; CHECK-NEXT: fsrm a0
496496
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -532,8 +532,8 @@ define <vscale x 2 x double> @vp_ceil_vv_nxv2f64(<vscale x 2 x double> %va, <vsc
532532
; CHECK-NEXT: vfabs.v v12, v8, v0.t
533533
; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, mu
534534
; CHECK-NEXT: vmflt.vf v10, v12, fa5, v0.t
535-
; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
536535
; CHECK-NEXT: fsrmi a0, 3
536+
; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
537537
; CHECK-NEXT: vmv1r.v v0, v10
538538
; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t
539539
; CHECK-NEXT: fsrm a0
@@ -576,8 +576,8 @@ define <vscale x 4 x double> @vp_ceil_vv_nxv4f64(<vscale x 4 x double> %va, <vsc
576576
; CHECK-NEXT: vfabs.v v16, v8, v0.t
577577
; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, mu
578578
; CHECK-NEXT: vmflt.vf v12, v16, fa5, v0.t
579-
; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma
580579
; CHECK-NEXT: fsrmi a0, 3
580+
; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma
581581
; CHECK-NEXT: vmv1r.v v0, v12
582582
; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t
583583
; CHECK-NEXT: fsrm a0
@@ -620,8 +620,8 @@ define <vscale x 7 x double> @vp_ceil_vv_nxv7f64(<vscale x 7 x double> %va, <vsc
620620
; CHECK-NEXT: vfabs.v v24, v8, v0.t
621621
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu
622622
; CHECK-NEXT: vmflt.vf v16, v24, fa5, v0.t
623-
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma
624623
; CHECK-NEXT: fsrmi a0, 3
624+
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma
625625
; CHECK-NEXT: vmv1r.v v0, v16
626626
; CHECK-NEXT: vfcvt.x.f.v v24, v8, v0.t
627627
; CHECK-NEXT: fsrm a0
@@ -664,8 +664,8 @@ define <vscale x 8 x double> @vp_ceil_vv_nxv8f64(<vscale x 8 x double> %va, <vsc
664664
; CHECK-NEXT: vfabs.v v24, v8, v0.t
665665
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu
666666
; CHECK-NEXT: vmflt.vf v16, v24, fa5, v0.t
667-
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma
668667
; CHECK-NEXT: fsrmi a0, 3
668+
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma
669669
; CHECK-NEXT: vmv1r.v v0, v16
670670
; CHECK-NEXT: vfcvt.x.f.v v24, v8, v0.t
671671
; CHECK-NEXT: fsrm a0
@@ -726,8 +726,8 @@ define <vscale x 16 x double> @vp_ceil_vv_nxv16f64(<vscale x 16 x double> %va, <
726726
; CHECK-NEXT: vfabs.v v8, v16, v0.t
727727
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu
728728
; CHECK-NEXT: vmflt.vf v25, v8, fa5, v0.t
729-
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma
730729
; CHECK-NEXT: fsrmi a2, 3
730+
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma
731731
; CHECK-NEXT: vmv1r.v v0, v25
732732
; CHECK-NEXT: vfcvt.x.f.v v8, v16, v0.t
733733
; CHECK-NEXT: fsrm a2
@@ -750,8 +750,8 @@ define <vscale x 16 x double> @vp_ceil_vv_nxv16f64(<vscale x 16 x double> %va, <
750750
; CHECK-NEXT: vfabs.v v16, v8, v0.t
751751
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu
752752
; CHECK-NEXT: vmflt.vf v24, v16, fa5, v0.t
753-
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma
754753
; CHECK-NEXT: fsrmi a0, 3
754+
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma
755755
; CHECK-NEXT: vmv1r.v v0, v24
756756
; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t
757757
; CHECK-NEXT: fsrm a0

‎llvm/test/CodeGen/RISCV/rvv/commutable.ll

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -720,8 +720,8 @@ declare <vscale x 1 x i64> @llvm.riscv.vaadd.nxv1i64.nxv1i64(<vscale x 1 x i64>,
720720
define <vscale x 1 x i64> @commutable_vaadd_vv(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, iXLen %2) nounwind {
721721
; CHECK-LABEL: commutable_vaadd_vv:
722722
; CHECK: # %bb.0: # %entry
723-
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
724723
; CHECK-NEXT: csrwi vxrm, 0
724+
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
725725
; CHECK-NEXT: vaadd.vv v8, v8, v9
726726
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma
727727
; CHECK-NEXT: vadd.vv v8, v8, v8
@@ -737,8 +737,8 @@ declare <vscale x 1 x i64> @llvm.riscv.vaadd.mask.nxv1i64.nxv1i64(<vscale x 1 x
737737
define <vscale x 1 x i64> @commutable_vaadd_vv_masked(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %mask, iXLen %2) {
738738
; CHECK-LABEL: commutable_vaadd_vv_masked:
739739
; CHECK: # %bb.0:
740-
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
741740
; CHECK-NEXT: csrwi vxrm, 0
741+
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
742742
; CHECK-NEXT: vaadd.vv v10, v8, v9, v0.t
743743
; CHECK-NEXT: vaadd.vv v8, v8, v9, v0.t
744744
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma
@@ -755,8 +755,8 @@ declare <vscale x 1 x i64> @llvm.riscv.vaaddu.nxv1i64.nxv1i64(<vscale x 1 x i64>
755755
define <vscale x 1 x i64> @commutable_vaaddu_vv(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, iXLen %2) nounwind {
756756
; CHECK-LABEL: commutable_vaaddu_vv:
757757
; CHECK: # %bb.0: # %entry
758-
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
759758
; CHECK-NEXT: csrwi vxrm, 0
759+
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
760760
; CHECK-NEXT: vaaddu.vv v8, v8, v9
761761
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma
762762
; CHECK-NEXT: vadd.vv v8, v8, v8
@@ -772,8 +772,8 @@ declare <vscale x 1 x i64> @llvm.riscv.vaaddu.mask.nxv1i64.nxv1i64(<vscale x 1 x
772772
define <vscale x 1 x i64> @commutable_vaaddu_vv_masked(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %mask, iXLen %2) {
773773
; CHECK-LABEL: commutable_vaaddu_vv_masked:
774774
; CHECK: # %bb.0:
775-
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
776775
; CHECK-NEXT: csrwi vxrm, 0
776+
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
777777
; CHECK-NEXT: vaaddu.vv v10, v8, v9, v0.t
778778
; CHECK-NEXT: vaaddu.vv v8, v8, v9, v0.t
779779
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma
@@ -790,8 +790,8 @@ declare <vscale x 1 x i64> @llvm.riscv.vsmul.nxv1i64.nxv1i64(<vscale x 1 x i64>,
790790
define <vscale x 1 x i64> @commutable_vsmul_vv(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, iXLen %2) nounwind {
791791
; CHECK-LABEL: commutable_vsmul_vv:
792792
; CHECK: # %bb.0: # %entry
793-
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
794793
; CHECK-NEXT: csrwi vxrm, 0
794+
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
795795
; CHECK-NEXT: vsmul.vv v8, v8, v9
796796
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma
797797
; CHECK-NEXT: vadd.vv v8, v8, v8
@@ -807,8 +807,8 @@ declare <vscale x 1 x i64> @llvm.riscv.vsmul.mask.nxv1i64.nxv1i64(<vscale x 1 x
807807
define <vscale x 1 x i64> @commutable_vsmul_vv_masked(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %mask, iXLen %2) {
808808
; CHECK-LABEL: commutable_vsmul_vv_masked:
809809
; CHECK: # %bb.0:
810-
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
811810
; CHECK-NEXT: csrwi vxrm, 0
811+
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
812812
; CHECK-NEXT: vsmul.vv v10, v8, v9, v0.t
813813
; CHECK-NEXT: vsmul.vv v8, v8, v9, v0.t
814814
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma

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