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RKSimonRKSimon
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[X86] Standardize VPSLLDQ/VPSRLDQ enum names (PR31079)
Tweak EVEX implementation names so it matches the other variants
1 parent ec93c75 commit 0ed79e9

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4 files changed

+32
-33
lines changed

4 files changed

+32
-33
lines changed

‎llvm/lib/Target/X86/MCTargetDesc/X86InstComments.cpp

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -669,14 +669,14 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
669669
case X86::PSLLDQri:
670670
case X86::VPSLLDQri:
671671
case X86::VPSLLDQYri:
672-
case X86::VPSLLDQZ128rr:
673-
case X86::VPSLLDQZ256rr:
674-
case X86::VPSLLDQZrr:
672+
case X86::VPSLLDQZ128ri:
673+
case X86::VPSLLDQZ256ri:
674+
case X86::VPSLLDQZri:
675675
Src1Name = getRegName(MI->getOperand(1).getReg());
676676
LLVM_FALLTHROUGH;
677-
case X86::VPSLLDQZ128rm:
678-
case X86::VPSLLDQZ256rm:
679-
case X86::VPSLLDQZrm:
677+
case X86::VPSLLDQZ128mi:
678+
case X86::VPSLLDQZ256mi:
679+
case X86::VPSLLDQZmi:
680680
DestName = getRegName(MI->getOperand(0).getReg());
681681
if (MI->getOperand(NumOperands - 1).isImm())
682682
DecodePSLLDQMask(getRegOperandNumElts(MI, 8, 0),
@@ -687,14 +687,14 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
687687
case X86::PSRLDQri:
688688
case X86::VPSRLDQri:
689689
case X86::VPSRLDQYri:
690-
case X86::VPSRLDQZ128rr:
691-
case X86::VPSRLDQZ256rr:
692-
case X86::VPSRLDQZrr:
690+
case X86::VPSRLDQZ128ri:
691+
case X86::VPSRLDQZ256ri:
692+
case X86::VPSRLDQZri:
693693
Src1Name = getRegName(MI->getOperand(1).getReg());
694694
LLVM_FALLTHROUGH;
695-
case X86::VPSRLDQZ128rm:
696-
case X86::VPSRLDQZ256rm:
697-
case X86::VPSRLDQZrm:
695+
case X86::VPSRLDQZ128mi:
696+
case X86::VPSRLDQZ256mi:
697+
case X86::VPSRLDQZmi:
698698
DestName = getRegName(MI->getOperand(0).getReg());
699699
if (MI->getOperand(NumOperands - 1).isImm())
700700
DecodePSRLDQMask(getRegOperandNumElts(MI, 8, 0),

‎llvm/lib/Target/X86/X86InstrAVX512.td

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -10972,16 +10972,15 @@ defm VSHUFPD: avx512_shufp<"vshufpd", avx512vl_i64_info, avx512vl_f64_info>, PD,
1097210972
// AVX-512 - Byte shift Left/Right
1097310973
//===----------------------------------------------------------------------===//
1097410974

10975-
// FIXME: The SSE/AVX names are PSLLDQri etc. - should we add the i here as well?
1097610975
multiclass avx512_shift_packed<bits<8> opc, SDNode OpNode, Format MRMr,
1097710976
Format MRMm, string OpcodeStr,
1097810977
X86FoldableSchedWrite sched, X86VectorVTInfo _>{
10979-
def rr : AVX512<opc, MRMr,
10978+
def ri : AVX512<opc, MRMr,
1098010979
(outs _.RC:$dst), (ins _.RC:$src1, u8imm:$src2),
1098110980
!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1098210981
[(set _.RC:$dst,(_.VT (OpNode _.RC:$src1, (i8 timm:$src2))))]>,
1098310982
Sched<[sched]>;
10984-
def rm : AVX512<opc, MRMm,
10983+
def mi : AVX512<opc, MRMm,
1098510984
(outs _.RC:$dst), (ins _.MemOp:$src1, u8imm:$src2),
1098610985
!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1098710986
[(set _.RC:$dst,(_.VT (OpNode

‎llvm/lib/Target/X86/X86InstrFoldTables.cpp

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1100,9 +1100,9 @@ static const X86MemoryFoldTableEntry MemoryFoldTable1[] = {
11001100
{ X86::VPSHUFLWZ256ri, X86::VPSHUFLWZ256mi, 0 },
11011101
{ X86::VPSHUFLWZri, X86::VPSHUFLWZmi, 0 },
11021102
{ X86::VPSHUFLWri, X86::VPSHUFLWmi, 0 },
1103-
{ X86::VPSLLDQZ128rr, X86::VPSLLDQZ128rm, 0 },
1104-
{ X86::VPSLLDQZ256rr, X86::VPSLLDQZ256rm, 0 },
1105-
{ X86::VPSLLDQZrr, X86::VPSLLDQZrm, 0 },
1103+
{ X86::VPSLLDQZ128ri, X86::VPSLLDQZ128mi, 0 },
1104+
{ X86::VPSLLDQZ256ri, X86::VPSLLDQZ256mi, 0 },
1105+
{ X86::VPSLLDQZri, X86::VPSLLDQZmi, 0 },
11061106
{ X86::VPSLLDZ128ri, X86::VPSLLDZ128mi, 0 },
11071107
{ X86::VPSLLDZ256ri, X86::VPSLLDZ256mi, 0 },
11081108
{ X86::VPSLLDZri, X86::VPSLLDZmi, 0 },
@@ -1121,9 +1121,9 @@ static const X86MemoryFoldTableEntry MemoryFoldTable1[] = {
11211121
{ X86::VPSRAWZ128ri, X86::VPSRAWZ128mi, 0 },
11221122
{ X86::VPSRAWZ256ri, X86::VPSRAWZ256mi, 0 },
11231123
{ X86::VPSRAWZri, X86::VPSRAWZmi, 0 },
1124-
{ X86::VPSRLDQZ128rr, X86::VPSRLDQZ128rm, 0 },
1125-
{ X86::VPSRLDQZ256rr, X86::VPSRLDQZ256rm, 0 },
1126-
{ X86::VPSRLDQZrr, X86::VPSRLDQZrm, 0 },
1124+
{ X86::VPSRLDQZ128ri, X86::VPSRLDQZ128mi, 0 },
1125+
{ X86::VPSRLDQZ256ri, X86::VPSRLDQZ256mi, 0 },
1126+
{ X86::VPSRLDQZri, X86::VPSRLDQZmi, 0 },
11271127
{ X86::VPSRLDZ128ri, X86::VPSRLDZ128mi, 0 },
11281128
{ X86::VPSRLDZ256ri, X86::VPSRLDZ256mi, 0 },
11291129
{ X86::VPSRLDZri, X86::VPSRLDZmi, 0 },

‎llvm/test/CodeGen/X86/evex-to-vex-compress.mir

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -620,7 +620,7 @@ body: |
620620
; CHECK: $ymm0 = VPSRAWYrr $ymm0, $xmm1
621621
$ymm0 = VPSRAWZ256rr $ymm0, $xmm1
622622
; CHECK: $ymm0 = VPSRLDQYri $ymm0, 7
623-
$ymm0 = VPSRLDQZ256rr $ymm0, 7
623+
$ymm0 = VPSRLDQZ256ri $ymm0, 7
624624
; CHECK: $ymm0 = VPSRLDYri $ymm0, 7
625625
$ymm0 = VPSRLDZ256ri $ymm0, 7
626626
; CHECK: $ymm0 = VPSRLDYrm $ymm0, $rip, 1, $rax, 0, $noreg
@@ -780,7 +780,7 @@ body: |
780780
; CHECK: $ymm0 = VPERMQYri $ymm0, 7
781781
$ymm0 = VPERMQZ256ri $ymm0, 7
782782
; CHECK: $ymm0 = VPSLLDQYri $ymm0, 14
783-
$ymm0 = VPSLLDQZ256rr $ymm0, 14
783+
$ymm0 = VPSLLDQZ256ri $ymm0, 14
784784
; CHECK: $ymm0 = VPSLLDYri $ymm0, 7
785785
$ymm0 = VPSLLDZ256ri $ymm0, 7
786786
; CHECK: $ymm0 = VPSLLDYrm $ymm0, $rip, 1, $rax, 0, $noreg
@@ -1610,7 +1610,7 @@ body: |
16101610
; CHECK: $xmm0 = VPSRAWrr $xmm0, $xmm0
16111611
$xmm0 = VPSRAWZ128rr $xmm0, $xmm0
16121612
; CHECK: $xmm0 = VPSRLDQri $xmm0, 14
1613-
$xmm0 = VPSRLDQZ128rr $xmm0, 14
1613+
$xmm0 = VPSRLDQZ128ri $xmm0, 14
16141614
; CHECK: $xmm0 = VPSRLDri $xmm0, 7
16151615
$xmm0 = VPSRLDZ128ri $xmm0, 7
16161616
; CHECK: $xmm0 = VPSRLDrm $xmm0, $rip, 1, $rax, 0, $noreg
@@ -1726,7 +1726,7 @@ body: |
17261726
; CHECK: $xmm0 = VPSHUFLWri $xmm0, -24
17271727
$xmm0 = VPSHUFLWZ128ri $xmm0, -24
17281728
; CHECK: $xmm0 = VPSLLDQri $xmm0, 7
1729-
$xmm0 = VPSLLDQZ128rr $xmm0, 7
1729+
$xmm0 = VPSLLDQZ128ri $xmm0, 7
17301730
; CHECK: $xmm0 = VSHUFPDrmi $xmm0, $rip, 1, $rax, 0, $noreg, -24
17311731
$xmm0 = VSHUFPDZ128rmi $xmm0, $rip, 1, $rax, 0, $noreg, -24
17321732
; CHECK: $xmm0 = VSHUFPDrri $xmm0, $xmm1, -24
@@ -2982,8 +2982,8 @@ body: |
29822982
$ymm16 = VPSRAWZ256rm $ymm16, $rip, 1, $rax, 0, $noreg
29832983
; CHECK: $ymm16 = VPSRAWZ256rr $ymm16, $xmm1
29842984
$ymm16 = VPSRAWZ256rr $ymm16, $xmm1
2985-
; CHECK: $ymm16 = VPSRLDQZ256rr $ymm16, 7
2986-
$ymm16 = VPSRLDQZ256rr $ymm16, 7
2985+
; CHECK: $ymm16 = VPSRLDQZ256ri $ymm16, 7
2986+
$ymm16 = VPSRLDQZ256ri $ymm16, 7
29872987
; CHECK: $ymm16 = VPSRLDZ256ri $ymm16, 7
29882988
$ymm16 = VPSRLDZ256ri $ymm16, 7
29892989
; CHECK: $ymm16 = VPSRLDZ256rm $ymm16, $rip, 1, $rax, 0, $noreg
@@ -3142,8 +3142,8 @@ body: |
31423142
$ymm16 = VPERMQZ256mi $rdi, 1, $noreg, 0, $noreg, 7
31433143
; CHECK: $ymm16 = VPERMQZ256ri $ymm16, 7
31443144
$ymm16 = VPERMQZ256ri $ymm16, 7
3145-
; CHECK: $ymm16 = VPSLLDQZ256rr $ymm16, 14
3146-
$ymm16 = VPSLLDQZ256rr $ymm16, 14
3145+
; CHECK: $ymm16 = VPSLLDQZ256ri $ymm16, 14
3146+
$ymm16 = VPSLLDQZ256ri $ymm16, 14
31473147
; CHECK: $ymm16 = VPSLLDZ256ri $ymm16, 7
31483148
$ymm16 = VPSLLDZ256ri $ymm16, 7
31493149
; CHECK: $ymm16 = VPSLLDZ256rm $ymm16, $rip, 1, $rax, 0, $noreg
@@ -3980,8 +3980,8 @@ body: |
39803980
$xmm16 = VPSRAWZ128rm $xmm16, $rip, 1, $rax, 0, $noreg
39813981
; CHECK: $xmm16 = VPSRAWZ128rr $xmm16, $xmm16
39823982
$xmm16 = VPSRAWZ128rr $xmm16, $xmm16
3983-
; CHECK: $xmm16 = VPSRLDQZ128rr $xmm16, 14
3984-
$xmm16 = VPSRLDQZ128rr $xmm16, 14
3983+
; CHECK: $xmm16 = VPSRLDQZ128ri $xmm16, 14
3984+
$xmm16 = VPSRLDQZ128ri $xmm16, 14
39853985
; CHECK: $xmm16 = VPSRLDZ128ri $xmm16, 7
39863986
$xmm16 = VPSRLDZ128ri $xmm16, 7
39873987
; CHECK: $xmm16 = VPSRLDZ128rm $xmm16, $rip, 1, $rax, 0, $noreg
@@ -4096,8 +4096,8 @@ body: |
40964096
$xmm16 = VPSHUFLWZ128mi $rdi, 1, $noreg, 0, $noreg, -24
40974097
; CHECK: $xmm16 = VPSHUFLWZ128ri $xmm16, -24
40984098
$xmm16 = VPSHUFLWZ128ri $xmm16, -24
4099-
; CHECK: $xmm16 = VPSLLDQZ128rr $xmm16, 1
4100-
$xmm16 = VPSLLDQZ128rr $xmm16, 1
4099+
; CHECK: $xmm16 = VPSLLDQZ128ri $xmm16, 1
4100+
$xmm16 = VPSLLDQZ128ri $xmm16, 1
41014101
; CHECK: $xmm16 = VSHUFPDZ128rmi $xmm16, $rip, 1, $rax, 0, $noreg, -24
41024102
$xmm16 = VSHUFPDZ128rmi $xmm16, $rip, 1, $rax, 0, $noreg, -24
41034103
; CHECK: $xmm16 = VSHUFPDZ128rri $xmm16, $xmm1, -24

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