- Move isBeforeLegalize before call to optimizeIncrementingWhile

- Add isSVEorStreamingSVEAvailable assert to LowerGET_ACTIVE_LANE_MASK
- Added more details to the comment in ISDOpcodes.h

Author: kmclaughlin-arm

llvm/include/llvm/CodeGen/ISDOpcodes.h

@@ -1524,10 +1524,13 @@ enum NodeType {
   // Operands: Mask
   VECTOR_FIND_LAST_ACTIVE,
 
-  // Creates a mask representing active and inactive
-  // vector lanes, active while base < trip count.
-  // Operands: Base, Trip Count
-  // Output: Mask
+  // GET_ACTIVE_LANE_MASK - this corrosponds to the llvm.get.active.lane.mask
+  // intrinsic. It creates a mask representing active and inactive vector
+  // lanes, active while Base + index < Trip Count. As with the intrinsic,
+  // the operands Base and Trip Count have the same scalar integer type and
+  // the internal addition of Base + index cannot overflow. However, the ISD
+  // node supports result types which are wider than i1, where the high
+  // bits conform to getBooleanContents similar to the SETCC operator.
   GET_ACTIVE_LANE_MASK,
 
   // llvm.clear_cache intrinsic

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

@@ -18140,13 +18140,13 @@ static SDValue performVecReduceAddCombineWithUADDLP(SDNode *N,
 static SDValue
 performActiveLaneMaskCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
                              const AArch64Subtarget *ST) {
+  if (DCI.isBeforeLegalize())
+    return SDValue();
+
   if (SDValue While = optimizeIncrementingWhile(N, DCI.DAG, /*IsSigned=*/false,
                                                 /*IsEqual=*/false))
     return While;
 
-  if (DCI.isBeforeLegalize())
-    return SDValue();
-
   if (!ST->hasSVE2p1())
     return SDValue();
 
@@ -29551,9 +29551,12 @@ AArch64TargetLowering::LowerGET_ACTIVE_LANE_MASK(SDValue Op,
   EVT VT = Op.getValueType();
   assert(VT.isFixedLengthVector() && "Expected fixed length vector type!");
 
-  // We can use the SVE whilelo instruction to lower this intrinsic by
-  // creating the appropriate sequence of scalable vector operations and
-  // then extracting a fixed-width subvector from the scalable vector.
+  auto &Subtarget = DAG.getSubtarget<AArch64Subtarget>();
+  assert(Subtarget.isSVEorStreamingSVEAvailable() &&
+         "Lowering fixed length get_active_lane_mask requires SVE!");
+
+  // There are no dedicated fixed-length instructions for GET_ACTIVE_LANE_MASK,
+  // but we can use SVE when available.
 
   SDLoc DL(Op);
   EVT ContainerVT = getContainerForFixedLengthVector(DAG, VT);