Address review and update tests

Author: bfavela

llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp

@@ -345,20 +345,19 @@ MachineInstr *SDWASrcOperand::potentialToConvert(const SIInstrInfo *TII,
       return nullptr;
     }
 
-
     for (MachineInstr &UseMI : getMRI()->use_nodbg_instructions(Reg->getReg())) {
-      // If there exist use of subreg of Reg then return nullptr
-      if (!isSameReg(UseMO, *Reg))
-        return nullptr;
-
-      // Check that all instructions the use Reg can be converted
+      // Check that all instructions that use Reg can be converted
       if (!isConvertibleToSDWA(UseMI, ST, TII)) {
         return nullptr;
       }
     }
+
     // Now that it's guaranteed all uses are legal, iterate over the uses again
     // to add them for later conversion.
     for (MachineOperand &UseMO : getMRI()->use_nodbg_operands(Reg->getReg())) {
+      // Should not get a subregister here
+      assert(isSameReg(UseMO, *Reg));
+
       SDWAOperandsMap& potentialMatchesMap = *PotentialMatches;
       MachineInstr* UseMI = UseMO.getParent();
       potentialMatchesMap[UseMI].push_back(this);

llvm/test/CodeGen/AMDGPU/llvm.fmuladd.f16.ll

@@ -659,31 +659,28 @@ define amdgpu_kernel void @fmuladd_v2f16(
 ; VI-FLUSH-NEXT:    s_mov_b32 s14, s10
 ; VI-FLUSH-NEXT:    s_mov_b32 s15, s11
 ; VI-FLUSH-NEXT:    s_waitcnt lgkmcnt(0)
+; VI-FLUSH-NEXT:    s_mov_b32 s12, s2
+; VI-FLUSH-NEXT:    s_mov_b32 s13, s3
 ; VI-FLUSH-NEXT:    s_mov_b32 s16, s4
 ; VI-FLUSH-NEXT:    s_mov_b32 s17, s5
+; VI-FLUSH-NEXT:    s_mov_b32 s18, s10
+; VI-FLUSH-NEXT:    s_mov_b32 s19, s11
 ; VI-FLUSH-NEXT:    s_mov_b32 s4, s6
 ; VI-FLUSH-NEXT:    s_mov_b32 s5, s7
 ; VI-FLUSH-NEXT:    s_mov_b32 s6, s10
 ; VI-FLUSH-NEXT:    s_mov_b32 s7, s11
-; VI-FLUSH-NEXT:    s_mov_b32 s12, s2
-; VI-FLUSH-NEXT:    s_mov_b32 s13, s3
-; VI-FLUSH-NEXT:    s_mov_b32 s18, s10
-; VI-FLUSH-NEXT:    s_mov_b32 s19, s11
-; VI-FLUSH-NEXT:    buffer_load_dword v0, off, s[4:7], 0
-; VI-FLUSH-NEXT:    buffer_load_dword v1, off, s[16:19], 0
-; VI-FLUSH-NEXT:    buffer_load_dword v2, off, s[12:15], 0
+; VI-FLUSH-NEXT:    buffer_load_dword v0, off, s[12:15], 0
+; VI-FLUSH-NEXT:    buffer_load_dword v1, off, s[4:7], 0
+; VI-FLUSH-NEXT:    buffer_load_dword v2, off, s[16:19], 0
 ; VI-FLUSH-NEXT:    s_mov_b32 s8, s0
 ; VI-FLUSH-NEXT:    s_mov_b32 s9, s1
-; VI-FLUSH-NEXT:    s_waitcnt vmcnt(2)
-; VI-FLUSH-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
 ; VI-FLUSH-NEXT:    s_waitcnt vmcnt(1)
-; VI-FLUSH-NEXT:    v_lshrrev_b32_e32 v4, 16, v1
+; VI-FLUSH-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
 ; VI-FLUSH-NEXT:    s_waitcnt vmcnt(0)
-; VI-FLUSH-NEXT:    v_lshrrev_b32_e32 v5, 16, v2
-; VI-FLUSH-NEXT:    v_mac_f16_e32 v3, v5, v4
+; VI-FLUSH-NEXT:    v_mac_f16_sdwa v3, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
 ; VI-FLUSH-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
-; VI-FLUSH-NEXT:    v_mac_f16_e32 v0, v2, v1
-; VI-FLUSH-NEXT:    v_or_b32_e32 v0, v0, v3
+; VI-FLUSH-NEXT:    v_mac_f16_e32 v1, v0, v2
+; VI-FLUSH-NEXT:    v_or_b32_e32 v0, v1, v3
 ; VI-FLUSH-NEXT:    buffer_store_dword v0, off, s[8:11], 0
 ; VI-FLUSH-NEXT:    s_endpgm
 ;

llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll

@@ -1557,8 +1557,7 @@ define amdgpu_kernel void @mac_v2half(ptr addrspace(1) %out, ptr addrspace(1) %i
 ; GFX89-NEXT:    s_waitcnt vmcnt(1)
 ; GFX89-NEXT:    v_lshrrev_b32_e32 v4, 16, v2
 ; GFX89-NEXT:    s_waitcnt vmcnt(0)
-; GFX89-NEXT:    v_lshrrev_b32_e32 v5, 16, v3
-; GFX89-NEXT:    v_mac_f16_sdwa v4, v5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX89-NEXT:    v_mac_f16_sdwa v4, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
 ; GFX89-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
 ; GFX89-NEXT:    v_mac_f16_e32 v2, v3, v2
 ; GFX89-NEXT:    v_or_b32_e32 v2, v2, v4