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[RISCV] update ctlz-sdnode.ll
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‎llvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll

Lines changed: 230 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
22
; RUN: llc -mtriple=riscv32 -mattr=+zve64x -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-ZVE64X,RV32,RV32I
33
; RUN: llc -mtriple=riscv64 -mattr=+zve64x -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-ZVE64X,RV64,RV64I
4-
; RUN: llc -mtriple=riscv32 -mattr=+zve64f,+f -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-F,RV32
5-
; RUN: llc -mtriple=riscv64 -mattr=+zve64f,+f -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-F,RV64
4+
; RUN: llc -mtriple=riscv32 -mattr=+zve64f,+f -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-F,RV32F
5+
; RUN: llc -mtriple=riscv64 -mattr=+zve64f,+f -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-F,RV64F
66
; RUN: llc -mtriple=riscv32 -mattr=+v,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-D,RV32
77
; RUN: llc -mtriple=riscv64 -mattr=+v,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-D,RV64
88
; RUN: llc -mtriple=riscv32 -mattr=+v,+zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB
@@ -1229,6 +1229,37 @@ define <vscale x 1 x i64> @ctlz_nxv1i64(<vscale x 1 x i64> %va) {
12291229
; RV64I-NEXT: vsrl.vx v8, v8, a0
12301230
; RV64I-NEXT: ret
12311231
;
1232+
; RV32F-LABEL: ctlz_nxv1i64:
1233+
; RV32F: # %bb.0:
1234+
; RV32F-NEXT: li a0, 190
1235+
; RV32F-NEXT: vsetvli a1, zero, e64, m1, ta, ma
1236+
; RV32F-NEXT: vmv.v.x v9, a0
1237+
; RV32F-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
1238+
; RV32F-NEXT: fsrmi a0, 1
1239+
; RV32F-NEXT: vfncvt.f.xu.w v10, v8
1240+
; RV32F-NEXT: vsrl.vi v8, v10, 23
1241+
; RV32F-NEXT: vwsubu.wv v9, v9, v8
1242+
; RV32F-NEXT: li a1, 64
1243+
; RV32F-NEXT: vsetvli zero, zero, e64, m1, ta, ma
1244+
; RV32F-NEXT: vminu.vx v8, v9, a1
1245+
; RV32F-NEXT: fsrm a0
1246+
; RV32F-NEXT: ret
1247+
;
1248+
; RV64F-LABEL: ctlz_nxv1i64:
1249+
; RV64F: # %bb.0:
1250+
; RV64F-NEXT: li a0, 190
1251+
; RV64F-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
1252+
; RV64F-NEXT: vmv.v.x v9, a0
1253+
; RV64F-NEXT: fsrmi a0, 1
1254+
; RV64F-NEXT: vfncvt.f.xu.w v10, v8
1255+
; RV64F-NEXT: vsrl.vi v8, v10, 23
1256+
; RV64F-NEXT: vwsubu.vv v10, v9, v8
1257+
; RV64F-NEXT: li a1, 64
1258+
; RV64F-NEXT: vsetvli zero, zero, e64, m1, ta, ma
1259+
; RV64F-NEXT: vminu.vx v8, v10, a1
1260+
; RV64F-NEXT: fsrm a0
1261+
; RV64F-NEXT: ret
1262+
;
12321263
; CHECK-D-LABEL: ctlz_nxv1i64:
12331264
; CHECK-D: # %bb.0:
12341265
; CHECK-D-NEXT: vsetvli a0, zero, e64, m1, ta, ma
@@ -1354,6 +1385,37 @@ define <vscale x 2 x i64> @ctlz_nxv2i64(<vscale x 2 x i64> %va) {
13541385
; RV64I-NEXT: vsrl.vx v8, v8, a0
13551386
; RV64I-NEXT: ret
13561387
;
1388+
; RV32F-LABEL: ctlz_nxv2i64:
1389+
; RV32F: # %bb.0:
1390+
; RV32F-NEXT: li a0, 190
1391+
; RV32F-NEXT: vsetvli a1, zero, e64, m2, ta, ma
1392+
; RV32F-NEXT: vmv.v.x v10, a0
1393+
; RV32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
1394+
; RV32F-NEXT: fsrmi a0, 1
1395+
; RV32F-NEXT: vfncvt.f.xu.w v12, v8
1396+
; RV32F-NEXT: vsrl.vi v8, v12, 23
1397+
; RV32F-NEXT: vwsubu.wv v10, v10, v8
1398+
; RV32F-NEXT: li a1, 64
1399+
; RV32F-NEXT: vsetvli zero, zero, e64, m2, ta, ma
1400+
; RV32F-NEXT: vminu.vx v8, v10, a1
1401+
; RV32F-NEXT: fsrm a0
1402+
; RV32F-NEXT: ret
1403+
;
1404+
; RV64F-LABEL: ctlz_nxv2i64:
1405+
; RV64F: # %bb.0:
1406+
; RV64F-NEXT: li a0, 190
1407+
; RV64F-NEXT: vsetvli a1, zero, e32, m1, ta, ma
1408+
; RV64F-NEXT: vmv.v.x v10, a0
1409+
; RV64F-NEXT: fsrmi a0, 1
1410+
; RV64F-NEXT: vfncvt.f.xu.w v11, v8
1411+
; RV64F-NEXT: vsrl.vi v8, v11, 23
1412+
; RV64F-NEXT: vwsubu.vv v12, v10, v8
1413+
; RV64F-NEXT: li a1, 64
1414+
; RV64F-NEXT: vsetvli zero, zero, e64, m2, ta, ma
1415+
; RV64F-NEXT: vminu.vx v8, v12, a1
1416+
; RV64F-NEXT: fsrm a0
1417+
; RV64F-NEXT: ret
1418+
;
13571419
; CHECK-D-LABEL: ctlz_nxv2i64:
13581420
; CHECK-D: # %bb.0:
13591421
; CHECK-D-NEXT: vsetvli a0, zero, e64, m2, ta, ma
@@ -1479,6 +1541,37 @@ define <vscale x 4 x i64> @ctlz_nxv4i64(<vscale x 4 x i64> %va) {
14791541
; RV64I-NEXT: vsrl.vx v8, v8, a0
14801542
; RV64I-NEXT: ret
14811543
;
1544+
; RV32F-LABEL: ctlz_nxv4i64:
1545+
; RV32F: # %bb.0:
1546+
; RV32F-NEXT: li a0, 190
1547+
; RV32F-NEXT: vsetvli a1, zero, e64, m4, ta, ma
1548+
; RV32F-NEXT: vmv.v.x v12, a0
1549+
; RV32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
1550+
; RV32F-NEXT: fsrmi a0, 1
1551+
; RV32F-NEXT: vfncvt.f.xu.w v16, v8
1552+
; RV32F-NEXT: vsrl.vi v8, v16, 23
1553+
; RV32F-NEXT: vwsubu.wv v12, v12, v8
1554+
; RV32F-NEXT: li a1, 64
1555+
; RV32F-NEXT: vsetvli zero, zero, e64, m4, ta, ma
1556+
; RV32F-NEXT: vminu.vx v8, v12, a1
1557+
; RV32F-NEXT: fsrm a0
1558+
; RV32F-NEXT: ret
1559+
;
1560+
; RV64F-LABEL: ctlz_nxv4i64:
1561+
; RV64F: # %bb.0:
1562+
; RV64F-NEXT: li a0, 190
1563+
; RV64F-NEXT: vsetvli a1, zero, e32, m2, ta, ma
1564+
; RV64F-NEXT: vmv.v.x v12, a0
1565+
; RV64F-NEXT: fsrmi a0, 1
1566+
; RV64F-NEXT: vfncvt.f.xu.w v14, v8
1567+
; RV64F-NEXT: vsrl.vi v8, v14, 23
1568+
; RV64F-NEXT: vwsubu.vv v16, v12, v8
1569+
; RV64F-NEXT: li a1, 64
1570+
; RV64F-NEXT: vsetvli zero, zero, e64, m4, ta, ma
1571+
; RV64F-NEXT: vminu.vx v8, v16, a1
1572+
; RV64F-NEXT: fsrm a0
1573+
; RV64F-NEXT: ret
1574+
;
14821575
; CHECK-D-LABEL: ctlz_nxv4i64:
14831576
; CHECK-D: # %bb.0:
14841577
; CHECK-D-NEXT: vsetvli a0, zero, e64, m4, ta, ma
@@ -1604,6 +1697,37 @@ define <vscale x 8 x i64> @ctlz_nxv8i64(<vscale x 8 x i64> %va) {
16041697
; RV64I-NEXT: vsrl.vx v8, v8, a0
16051698
; RV64I-NEXT: ret
16061699
;
1700+
; RV32F-LABEL: ctlz_nxv8i64:
1701+
; RV32F: # %bb.0:
1702+
; RV32F-NEXT: li a0, 190
1703+
; RV32F-NEXT: vsetvli a1, zero, e64, m8, ta, ma
1704+
; RV32F-NEXT: vmv.v.x v16, a0
1705+
; RV32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma
1706+
; RV32F-NEXT: fsrmi a0, 1
1707+
; RV32F-NEXT: vfncvt.f.xu.w v24, v8
1708+
; RV32F-NEXT: vsrl.vi v8, v24, 23
1709+
; RV32F-NEXT: vwsubu.wv v16, v16, v8
1710+
; RV32F-NEXT: li a1, 64
1711+
; RV32F-NEXT: vsetvli zero, zero, e64, m8, ta, ma
1712+
; RV32F-NEXT: vminu.vx v8, v16, a1
1713+
; RV32F-NEXT: fsrm a0
1714+
; RV32F-NEXT: ret
1715+
;
1716+
; RV64F-LABEL: ctlz_nxv8i64:
1717+
; RV64F: # %bb.0:
1718+
; RV64F-NEXT: li a0, 190
1719+
; RV64F-NEXT: vsetvli a1, zero, e32, m4, ta, ma
1720+
; RV64F-NEXT: vmv.v.x v16, a0
1721+
; RV64F-NEXT: fsrmi a0, 1
1722+
; RV64F-NEXT: vfncvt.f.xu.w v20, v8
1723+
; RV64F-NEXT: vsrl.vi v8, v20, 23
1724+
; RV64F-NEXT: vwsubu.vv v24, v16, v8
1725+
; RV64F-NEXT: li a1, 64
1726+
; RV64F-NEXT: vsetvli zero, zero, e64, m8, ta, ma
1727+
; RV64F-NEXT: vminu.vx v8, v24, a1
1728+
; RV64F-NEXT: fsrm a0
1729+
; RV64F-NEXT: ret
1730+
;
16071731
; CHECK-D-LABEL: ctlz_nxv8i64:
16081732
; CHECK-D: # %bb.0:
16091733
; CHECK-D-NEXT: vsetvli a0, zero, e64, m8, ta, ma
@@ -2771,6 +2895,32 @@ define <vscale x 1 x i64> @ctlz_zero_undef_nxv1i64(<vscale x 1 x i64> %va) {
27712895
; RV64I-NEXT: vsrl.vx v8, v8, a0
27722896
; RV64I-NEXT: ret
27732897
;
2898+
; RV32F-LABEL: ctlz_zero_undef_nxv1i64:
2899+
; RV32F: # %bb.0:
2900+
; RV32F-NEXT: li a0, 190
2901+
; RV32F-NEXT: vsetvli a1, zero, e64, m1, ta, ma
2902+
; RV32F-NEXT: vmv.v.x v9, a0
2903+
; RV32F-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
2904+
; RV32F-NEXT: fsrmi a0, 1
2905+
; RV32F-NEXT: vfncvt.f.xu.w v10, v8
2906+
; RV32F-NEXT: vsrl.vi v8, v10, 23
2907+
; RV32F-NEXT: vwsubu.wv v9, v9, v8
2908+
; RV32F-NEXT: fsrm a0
2909+
; RV32F-NEXT: vmv1r.v v8, v9
2910+
; RV32F-NEXT: ret
2911+
;
2912+
; RV64F-LABEL: ctlz_zero_undef_nxv1i64:
2913+
; RV64F: # %bb.0:
2914+
; RV64F-NEXT: li a0, 190
2915+
; RV64F-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
2916+
; RV64F-NEXT: vmv.v.x v9, a0
2917+
; RV64F-NEXT: fsrmi a0, 1
2918+
; RV64F-NEXT: vfncvt.f.xu.w v10, v8
2919+
; RV64F-NEXT: vsrl.vi v10, v10, 23
2920+
; RV64F-NEXT: vwsubu.vv v8, v9, v10
2921+
; RV64F-NEXT: fsrm a0
2922+
; RV64F-NEXT: ret
2923+
;
27742924
; CHECK-D-LABEL: ctlz_zero_undef_nxv1i64:
27752925
; CHECK-D: # %bb.0:
27762926
; CHECK-D-NEXT: vsetvli a0, zero, e64, m1, ta, ma
@@ -2893,6 +3043,32 @@ define <vscale x 2 x i64> @ctlz_zero_undef_nxv2i64(<vscale x 2 x i64> %va) {
28933043
; RV64I-NEXT: vsrl.vx v8, v8, a0
28943044
; RV64I-NEXT: ret
28953045
;
3046+
; RV32F-LABEL: ctlz_zero_undef_nxv2i64:
3047+
; RV32F: # %bb.0:
3048+
; RV32F-NEXT: li a0, 190
3049+
; RV32F-NEXT: vsetvli a1, zero, e64, m2, ta, ma
3050+
; RV32F-NEXT: vmv.v.x v10, a0
3051+
; RV32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
3052+
; RV32F-NEXT: fsrmi a0, 1
3053+
; RV32F-NEXT: vfncvt.f.xu.w v12, v8
3054+
; RV32F-NEXT: vsrl.vi v8, v12, 23
3055+
; RV32F-NEXT: vwsubu.wv v10, v10, v8
3056+
; RV32F-NEXT: fsrm a0
3057+
; RV32F-NEXT: vmv2r.v v8, v10
3058+
; RV32F-NEXT: ret
3059+
;
3060+
; RV64F-LABEL: ctlz_zero_undef_nxv2i64:
3061+
; RV64F: # %bb.0:
3062+
; RV64F-NEXT: li a0, 190
3063+
; RV64F-NEXT: vsetvli a1, zero, e32, m1, ta, ma
3064+
; RV64F-NEXT: vmv.v.x v10, a0
3065+
; RV64F-NEXT: fsrmi a0, 1
3066+
; RV64F-NEXT: vfncvt.f.xu.w v11, v8
3067+
; RV64F-NEXT: vsrl.vi v11, v11, 23
3068+
; RV64F-NEXT: vwsubu.vv v8, v10, v11
3069+
; RV64F-NEXT: fsrm a0
3070+
; RV64F-NEXT: ret
3071+
;
28963072
; CHECK-D-LABEL: ctlz_zero_undef_nxv2i64:
28973073
; CHECK-D: # %bb.0:
28983074
; CHECK-D-NEXT: vsetvli a0, zero, e64, m2, ta, ma
@@ -3015,6 +3191,32 @@ define <vscale x 4 x i64> @ctlz_zero_undef_nxv4i64(<vscale x 4 x i64> %va) {
30153191
; RV64I-NEXT: vsrl.vx v8, v8, a0
30163192
; RV64I-NEXT: ret
30173193
;
3194+
; RV32F-LABEL: ctlz_zero_undef_nxv4i64:
3195+
; RV32F: # %bb.0:
3196+
; RV32F-NEXT: li a0, 190
3197+
; RV32F-NEXT: vsetvli a1, zero, e64, m4, ta, ma
3198+
; RV32F-NEXT: vmv.v.x v12, a0
3199+
; RV32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
3200+
; RV32F-NEXT: fsrmi a0, 1
3201+
; RV32F-NEXT: vfncvt.f.xu.w v16, v8
3202+
; RV32F-NEXT: vsrl.vi v8, v16, 23
3203+
; RV32F-NEXT: vwsubu.wv v12, v12, v8
3204+
; RV32F-NEXT: fsrm a0
3205+
; RV32F-NEXT: vmv4r.v v8, v12
3206+
; RV32F-NEXT: ret
3207+
;
3208+
; RV64F-LABEL: ctlz_zero_undef_nxv4i64:
3209+
; RV64F: # %bb.0:
3210+
; RV64F-NEXT: li a0, 190
3211+
; RV64F-NEXT: vsetvli a1, zero, e32, m2, ta, ma
3212+
; RV64F-NEXT: vmv.v.x v12, a0
3213+
; RV64F-NEXT: fsrmi a0, 1
3214+
; RV64F-NEXT: vfncvt.f.xu.w v14, v8
3215+
; RV64F-NEXT: vsrl.vi v14, v14, 23
3216+
; RV64F-NEXT: vwsubu.vv v8, v12, v14
3217+
; RV64F-NEXT: fsrm a0
3218+
; RV64F-NEXT: ret
3219+
;
30183220
; CHECK-D-LABEL: ctlz_zero_undef_nxv4i64:
30193221
; CHECK-D: # %bb.0:
30203222
; CHECK-D-NEXT: vsetvli a0, zero, e64, m4, ta, ma
@@ -3137,6 +3339,32 @@ define <vscale x 8 x i64> @ctlz_zero_undef_nxv8i64(<vscale x 8 x i64> %va) {
31373339
; RV64I-NEXT: vsrl.vx v8, v8, a0
31383340
; RV64I-NEXT: ret
31393341
;
3342+
; RV32F-LABEL: ctlz_zero_undef_nxv8i64:
3343+
; RV32F: # %bb.0:
3344+
; RV32F-NEXT: vmv8r.v v16, v8
3345+
; RV32F-NEXT: li a0, 190
3346+
; RV32F-NEXT: vsetvli a1, zero, e64, m8, ta, ma
3347+
; RV32F-NEXT: vmv.v.x v8, a0
3348+
; RV32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma
3349+
; RV32F-NEXT: fsrmi a0, 1
3350+
; RV32F-NEXT: vfncvt.f.xu.w v24, v16
3351+
; RV32F-NEXT: vsrl.vi v16, v24, 23
3352+
; RV32F-NEXT: vwsubu.wv v8, v8, v16
3353+
; RV32F-NEXT: fsrm a0
3354+
; RV32F-NEXT: ret
3355+
;
3356+
; RV64F-LABEL: ctlz_zero_undef_nxv8i64:
3357+
; RV64F: # %bb.0:
3358+
; RV64F-NEXT: li a0, 190
3359+
; RV64F-NEXT: vsetvli a1, zero, e32, m4, ta, ma
3360+
; RV64F-NEXT: vmv.v.x v16, a0
3361+
; RV64F-NEXT: fsrmi a0, 1
3362+
; RV64F-NEXT: vfncvt.f.xu.w v20, v8
3363+
; RV64F-NEXT: vsrl.vi v20, v20, 23
3364+
; RV64F-NEXT: vwsubu.vv v8, v16, v20
3365+
; RV64F-NEXT: fsrm a0
3366+
; RV64F-NEXT: ret
3367+
;
31403368
; CHECK-D-LABEL: ctlz_zero_undef_nxv8i64:
31413369
; CHECK-D: # %bb.0:
31423370
; CHECK-D-NEXT: vsetvli a0, zero, e64, m8, ta, ma

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