Remove commented code.

Author: Leon Clark

llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

@@ -1270,14 +1270,6 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
     .custom();
 
   // The 64-bit versions produce 32-bit results, but only on the SALU.
-//  getActionDefinitionsBuilder({G_CTLZ_ZERO_UNDEF, G_CTTZ_ZERO_UNDEF})
-//    .legalFor({{S32, S32}, {S32, S64}})
-//    .clampScalar(0, S32, S32)
-//    .clampScalar(1, S32, S64)
-//    .scalarize(0)
-//    .widenScalarToNextPow2(0, 32)
-//    .widenScalarToNextPow2(1, 32);
-
   getActionDefinitionsBuilder(G_CTLZ_ZERO_UNDEF)
     .legalFor({{S32, S32}, {S32, S64}})
     .customFor({{S32, S8}, {S32, S16}})
@@ -1286,12 +1278,6 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
     .scalarize(0)
     .widenScalarToNextPow2(0, 32)
     .widenScalarToNextPow2(1, 32);
-//    .custom();
-
-//    .legalFor({S32})
-//    .customFor({S64})
-//    .clampScalar(0, S32, S64)
-//    .scalarize(0);
 
   getActionDefinitionsBuilder(G_CTTZ_ZERO_UNDEF)
     .legalFor({{S32, S32}, {S32, S64}})
@@ -4187,10 +4173,6 @@ bool AMDGPULegalizerInfo::legalizeCTLZ_ZERO_UNDEF(MachineInstr &MI,
   B.buildInstr(AMDGPU::G_AMDGPU_FFBH_U32, {Dst}, {Src});
   MI.eraseFromParent();
   return true;
-
-  // LocalAccum = B.buildZExt(S32, CarryIn[0]).getReg(0);
-  // auto ShiftAmt = B.buildConstant(S32, Shift);
-  // AndMaskSrc = B.buildLShr(S32, LiveIn, ShiftAmt).getReg(0);
 }
 
 // Check that this is a G_XOR x, -1