[GlobalISel] Treat shift amounts as unsigned in matchShiftImmedChain

A miscompilation issue in the GISel pre-legalization
phase has been addressed with improved routines.

Fixes: #71440.

Author: antoniofrighetto

llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp

@@ -1557,7 +1557,7 @@ bool CombinerHelper::matchShiftImmedChain(MachineInstr &MI,
 
   // Pass the combined immediate to the apply function.
   MatchInfo.Imm =
-      (MaybeImmVal->Value.getSExtValue() + MaybeImm2Val->Value).getSExtValue();
+      (MaybeImmVal->Value.getZExtValue() + MaybeImm2Val->Value).getZExtValue();
   MatchInfo.Reg = Base;
 
   // There is no simple replacement for a saturating unsigned left shift that

llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-trivial-arith.mir

@@ -463,3 +463,28 @@ body:             |
     RET_ReallyLR implicit $x0
 
 ...
+---
+name:            udiv_of_sext
+alignment:       4
+tracksRegLiveness: true
+liveins:
+  - { reg: '$w0' }
+body:             |
+  bb.1:
+    liveins: $w0
+
+    ; CHECK-LABEL: name: udiv_of_sext
+    ; CHECK: liveins: $w0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+    ; CHECK-NEXT: $w0 = COPY [[C]](s32)
+    ; CHECK-NEXT: RET_ReallyLR implicit $w0
+    %2:_(s1) = G_CONSTANT i1 true
+    %4:_(s2) = G_CONSTANT i2 1
+    %3:_(s2) = G_SEXT %2:_(s1)
+    %5:_(s2) = G_UDIV %4:_, %3:_
+    %6:_(s32) = G_ANYEXT %5:_(s2)
+    $w0 = COPY %6:_(s32)
+    RET_ReallyLR implicit $w0
+
+...