Skip to content

Commit 1053b3e

Browse files
topperctopperc
committed
[RISCV][GISel] Stop promoting s32 G_SHL/ASHR/LSHR shift amount to s64 on RV64.
There are no SelectionDAG patterns to share. GISel has its own patterns since it considers s32 a legal type and SDAG does not.
1 parent 4e2efea commit 1053b3e

20 files changed

+496
-537
lines changed

‎llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp

Lines changed: 2 additions & 33 deletions
Original file line numberDiff line numberDiff line change
@@ -158,14 +158,12 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
158158
.lower();
159159

160160
auto &ShiftActions = getActionDefinitionsBuilder({G_ASHR, G_LSHR, G_SHL});
161-
if (ST.is64Bit())
162-
ShiftActions.customFor({{s32, s32}});
163-
ShiftActions.legalFor({{s32, s32}, {s32, sXLen}, {sXLen, sXLen}})
161+
ShiftActions.legalFor({{s32, s32}, {sXLen, sXLen}})
164162
.widenScalarToNextPow2(0)
165163
.clampScalar(1, s32, sXLen)
166164
.clampScalar(0, s32, sXLen)
167165
.minScalarSameAs(1, 0)
168-
.widenScalarToNextPow2(1);
166+
.maxScalarSameAs(1, 0);
169167

170168
auto &ExtActions =
171169
getActionDefinitionsBuilder({G_ZEXT, G_SEXT, G_ANYEXT})
@@ -656,30 +654,6 @@ bool RISCVLegalizerInfo::legalizeIntrinsic(LegalizerHelper &Helper,
656654
}
657655
}
658656

659-
bool RISCVLegalizerInfo::legalizeShlAshrLshr(
660-
MachineInstr &MI, MachineIRBuilder &MIRBuilder,
661-
GISelChangeObserver &Observer) const {
662-
assert(MI.getOpcode() == TargetOpcode::G_ASHR ||
663-
MI.getOpcode() == TargetOpcode::G_LSHR ||
664-
MI.getOpcode() == TargetOpcode::G_SHL);
665-
MachineRegisterInfo &MRI = *MIRBuilder.getMRI();
666-
// If the shift amount is a G_CONSTANT, promote it to a 64 bit type so the
667-
// imported patterns can select it later. Either way, it will be legal.
668-
Register AmtReg = MI.getOperand(2).getReg();
669-
auto VRegAndVal = getIConstantVRegValWithLookThrough(AmtReg, MRI);
670-
if (!VRegAndVal)
671-
return true;
672-
// Check the shift amount is in range for an immediate form.
673-
uint64_t Amount = VRegAndVal->Value.getZExtValue();
674-
if (Amount > 31)
675-
return true; // This will have to remain a register variant.
676-
auto ExtCst = MIRBuilder.buildConstant(LLT::scalar(64), Amount);
677-
Observer.changingInstr(MI);
678-
MI.getOperand(2).setReg(ExtCst.getReg(0));
679-
Observer.changedInstr(MI);
680-
return true;
681-
}
682-
683657
bool RISCVLegalizerInfo::legalizeVAStart(MachineInstr &MI,
684658
MachineIRBuilder &MIRBuilder) const {
685659
// Stores the address of the VarArgsFrameIndex slot into the memory location
@@ -1054,7 +1028,6 @@ bool RISCVLegalizerInfo::legalizeCustom(
10541028
LostDebugLocObserver &LocObserver) const {
10551029
MachineIRBuilder &MIRBuilder = Helper.MIRBuilder;
10561030
MachineRegisterInfo &MRI = *MIRBuilder.getMRI();
1057-
GISelChangeObserver &Observer = Helper.Observer;
10581031
MachineFunction &MF = *MI.getParent()->getParent();
10591032
switch (MI.getOpcode()) {
10601033
default:
@@ -1073,10 +1046,6 @@ bool RISCVLegalizerInfo::legalizeCustom(
10731046
return true;
10741047
return Helper.lowerConstant(MI);
10751048
}
1076-
case TargetOpcode::G_SHL:
1077-
case TargetOpcode::G_ASHR:
1078-
case TargetOpcode::G_LSHR:
1079-
return legalizeShlAshrLshr(MI, MIRBuilder, Observer);
10801049
case TargetOpcode::G_SEXT_INREG: {
10811050
LLT DstTy = MRI.getType(MI.getOperand(0).getReg());
10821051
int64_t SizeInBits = MI.getOperand(2).getImm();

‎llvm/lib/Target/RISCV/RISCVGISel.td

Lines changed: 10 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -95,10 +95,6 @@ def : Pat<(XLenVT (sub GPR:$rs1, simm12Plus1:$imm)),
9595
let Predicates = [IsRV64] in {
9696
def : Pat<(i32 (sub GPR:$rs1, simm12Plus1i32:$imm)),
9797
(ADDIW GPR:$rs1, (i64 (NegImm $imm)))>;
98-
99-
def : Pat<(i32 (shl GPR:$rs1, (i32 GPR:$rs2))), (SLLW GPR:$rs1, GPR:$rs2)>;
100-
def : Pat<(i32 (sra GPR:$rs1, (i32 GPR:$rs2))), (SRAW GPR:$rs1, GPR:$rs2)>;
101-
def : Pat<(i32 (srl GPR:$rs1, (i32 GPR:$rs2))), (SRLW GPR:$rs1, GPR:$rs2)>;
10298
}
10399

104100
// Ptr type used in patterns with GlobalISelEmitter
@@ -196,9 +192,9 @@ def : PatGprGpr<sub, SUBW, i32, i32>;
196192
def : PatGprGpr<and, AND, i32, i32>;
197193
def : PatGprGpr<or, OR, i32, i32>;
198194
def : PatGprGpr<xor, XOR, i32, i32>;
199-
def : PatGprGpr<shiftopw<shl>, SLLW, i32, i64>;
200-
def : PatGprGpr<shiftopw<srl>, SRLW, i32, i64>;
201-
def : PatGprGpr<shiftopw<sra>, SRAW, i32, i64>;
195+
def : PatGprGpr<shl, SLLW, i32, i32>;
196+
def : PatGprGpr<srl, SRLW, i32, i32>;
197+
def : PatGprGpr<sra, SRAW, i32, i32>;
202198

203199
def : Pat<(i32 (add GPR:$rs1, simm12i32:$imm)),
204200
(ADDIW GPR:$rs1, (i64 (as_i64imm $imm)))>;
@@ -209,9 +205,12 @@ def : Pat<(i32 (or GPR:$rs1, simm12i32:$imm)),
209205
def : Pat<(i32 (xor GPR:$rs1, simm12i32:$imm)),
210206
(XORI GPR:$rs1, (i64 (as_i64imm $imm)))>;
211207

212-
def : PatGprImm<shl, SLLIW, uimm5, i32>;
213-
def : PatGprImm<srl, SRLIW, uimm5, i32>;
214-
def : PatGprImm<sra, SRAIW, uimm5, i32>;
208+
def : Pat<(i32 (shl GPR:$rs1, uimm5i32:$imm)),
209+
(SLLIW GPR:$rs1, (i64 (as_i64imm $imm)))>;
210+
def : Pat<(i32 (srl GPR:$rs1, uimm5i32:$imm)),
211+
(SRLIW GPR:$rs1, (i64 (as_i64imm $imm)))>;
212+
def : Pat<(i32 (sra GPR:$rs1, uimm5i32:$imm)),
213+
(SRAIW GPR:$rs1, (i64 (as_i64imm $imm)))>;
215214

216215
def : Pat<(i32 (and GPR:$rs, TrailingOnesMask:$mask)),
217216
(SRLI (i32 (SLLI $rs, (i64 (XLenSubTrailingOnes $mask)))),
@@ -372,7 +371,7 @@ def : Pat<(zext GPR:$src), (ADD_UW GPR:$src, (XLenVT X0))>;
372371

373372
foreach i = {1,2,3} in {
374373
defvar shxadd = !cast<Instruction>("SH"#i#"ADD");
375-
def : Pat<(i32 (add_like_non_imm12 (shl GPR:$rs1, (i64 i)), GPR:$rs2)),
374+
def : Pat<(i32 (add_like_non_imm12 (shl GPR:$rs1, (i32 i)), GPR:$rs2)),
376375
(shxadd GPR:$rs1, GPR:$rs2)>;
377376
def : Pat<(i32 (riscv_shl_add GPR:$rs1, (i32 i), GPR:$rs2)),
378377
(shxadd GPR:$rs1, GPR:$rs2)>;

‎llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu-rv64.mir

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -245,8 +245,8 @@ body: |
245245
; RV64I-NEXT: PseudoRET implicit $x10
246246
%0:gprb(s64) = COPY $x10
247247
%1:gprb(s32) = G_TRUNC %0(s64)
248-
%2:gprb(s64) = G_CONSTANT i64 31
249-
%3:gprb(s32) = G_SHL %1, %2(s64)
248+
%2:gprb(s32) = G_CONSTANT i32 31
249+
%3:gprb(s32) = G_SHL %1, %2
250250
%4:gprb(s64) = G_ANYEXT %3(s32)
251251
$x10 = COPY %4(s64)
252252
PseudoRET implicit $x10
@@ -297,8 +297,8 @@ body: |
297297
; RV64I-NEXT: PseudoRET implicit $x10
298298
%0:gprb(s64) = COPY $x10
299299
%1:gprb(s32) = G_TRUNC %0(s64)
300-
%2:gprb(s64) = G_CONSTANT i64 31
301-
%3:gprb(s32) = G_ASHR %1, %2(s64)
300+
%2:gprb(s32) = G_CONSTANT i32 31
301+
%3:gprb(s32) = G_ASHR %1, %2
302302
%4:gprb(s64) = G_ANYEXT %3(s32)
303303
$x10 = COPY %4(s64)
304304
PseudoRET implicit $x10
@@ -349,8 +349,8 @@ body: |
349349
; RV64I-NEXT: PseudoRET implicit $x10
350350
%0:gprb(s64) = COPY $x10
351351
%1:gprb(s32) = G_TRUNC %0(s64)
352-
%2:gprb(s64) = G_CONSTANT i64 31
353-
%3:gprb(s32) = G_LSHR %1, %2(s64)
352+
%2:gprb(s32) = G_CONSTANT i32 31
353+
%3:gprb(s32) = G_LSHR %1, %2
354354
%4:gprb(s64) = G_ANYEXT %3(s32)
355355
$x10 = COPY %4(s64)
356356
PseudoRET implicit $x10

‎llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/zba-rv64.mir

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -269,7 +269,7 @@ body: |
269269
%1:gprb(s64) = COPY $x11
270270
%2:gprb(s32) = G_TRUNC %0
271271
%3:gprb(s32) = G_TRUNC %1
272-
%4:gprb(s64) = G_CONSTANT i64 1
272+
%4:gprb(s32) = G_CONSTANT i32 1
273273
%5:gprb(s32) = G_SHL %2, %4
274274
%6:gprb(s32) = G_ADD %5, %3
275275
%7:gprb(s64) = G_ANYEXT %6
@@ -295,7 +295,7 @@ body: |
295295
%1:gprb(s64) = COPY $x11
296296
%2:gprb(s32) = G_TRUNC %0
297297
%3:gprb(s32) = G_TRUNC %1
298-
%4:gprb(s64) = G_CONSTANT i64 2
298+
%4:gprb(s32) = G_CONSTANT i32 2
299299
%5:gprb(s32) = G_SHL %2, %4
300300
%6:gprb(s32) = G_ADD %5, %3
301301
%7:gprb(s64) = G_ANYEXT %6
@@ -321,7 +321,7 @@ body: |
321321
%1:gprb(s64) = COPY $x11
322322
%2:gprb(s32) = G_TRUNC %0
323323
%3:gprb(s32) = G_TRUNC %1
324-
%4:gprb(s64) = G_CONSTANT i64 3
324+
%4:gprb(s32) = G_CONSTANT i32 3
325325
%5:gprb(s32) = G_SHL %2, %4
326326
%6:gprb(s32) = G_ADD %5, %3
327327
%7:gprb(s64) = G_ANYEXT %6

‎llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-abs-rv64.mir

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -11,12 +11,12 @@ body: |
1111
; RV64I-LABEL: name: abs_i8
1212
; RV64I: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
1313
; RV64I-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s64) = G_ASSERT_ZEXT [[COPY]], 8
14+
; RV64I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
1415
; RV64I-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[ASSERT_ZEXT]](s64)
15-
; RV64I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 24
16-
; RV64I-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC]], [[C]](s64)
17-
; RV64I-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s64)
18-
; RV64I-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 7
19-
; RV64I-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[C1]](s64)
16+
; RV64I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
17+
; RV64I-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC]], [[C1]](s32)
18+
; RV64I-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32)
19+
; RV64I-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[C]](s32)
2020
; RV64I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[TRUNC]](s32)
2121
; RV64I-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY1]], [[ASHR1]]
2222
; RV64I-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[ADD]], [[ASHR1]]
@@ -52,9 +52,9 @@ body: |
5252
; RV64I-LABEL: name: abs_i16
5353
; RV64I: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
5454
; RV64I-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(s64) = G_ASSERT_SEXT [[COPY]], 16
55+
; RV64I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
5556
; RV64I-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[ASSERT_SEXT]](s64)
56-
; RV64I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 15
57-
; RV64I-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[TRUNC]], [[C]](s64)
57+
; RV64I-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[TRUNC]], [[C]](s32)
5858
; RV64I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[TRUNC]](s32)
5959
; RV64I-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY1]], [[ASHR]]
6060
; RV64I-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[ADD]], [[ASHR]]
@@ -90,8 +90,8 @@ body: |
9090
; RV64I: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
9191
; RV64I-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(s64) = G_ASSERT_SEXT [[COPY]], 32
9292
; RV64I-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[ASSERT_SEXT]](s64)
93-
; RV64I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 31
94-
; RV64I-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[TRUNC]], [[C]](s64)
93+
; RV64I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
94+
; RV64I-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[TRUNC]], [[C]](s32)
9595
; RV64I-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[TRUNC]], [[ASHR]]
9696
; RV64I-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[ADD]], [[ASHR]]
9797
; RV64I-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[XOR]](s32)

‎llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ashr-rv64.mir

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -12,9 +12,9 @@ body: |
1212
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
1313
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
1414
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
15-
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 24
16-
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC1]], [[C1]](s64)
17-
; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s64)
15+
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
16+
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC1]], [[C1]](s32)
17+
; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32)
1818
; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[AND]](s32)
1919
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ASHR1]](s32)
2020
; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
@@ -40,9 +40,9 @@ body: |
4040
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32767
4141
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
4242
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
43-
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 17
44-
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC1]], [[C1]](s64)
45-
; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s64)
43+
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 17
44+
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC1]], [[C1]](s32)
45+
; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32)
4646
; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[AND]](s32)
4747
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ASHR1]](s32)
4848
; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
@@ -68,9 +68,9 @@ body: |
6868
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
6969
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
7070
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
71-
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
72-
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC1]], [[C1]](s64)
73-
; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s64)
71+
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
72+
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC1]], [[C1]](s32)
73+
; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32)
7474
; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[AND]](s32)
7575
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ASHR1]](s32)
7676
; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)

0 commit comments

Comments
 (0)