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[AArch64][GlobalISel] Legalize BSWAP for Vector Types (#80036)
Add support of i16 vector operation for BSWAP and change to TableGen to select instructions Handle vector types that are smaller/larger than legal for BSWAP
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6 files changed

+196
-92
lines changed

6 files changed

+196
-92
lines changed

‎llvm/lib/Target/AArch64/AArch64InstrInfo.td

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -5166,6 +5166,18 @@ def : Pat<(v8i16 (concat_vectors
51665166
(v4i32 VImm8000)))))),
51675167
(SQXTNv8i16 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Vd, dsub), V128:$Vn)>;
51685168

5169+
// Select BSWAP vector instructions into REV instructions
5170+
def : Pat<(v4i16 (bswap (v4i16 V64:$Rn))),
5171+
(v4i16 (REV16v8i8 (v4i16 V64:$Rn)))>;
5172+
def : Pat<(v8i16 (bswap (v8i16 V128:$Rn))),
5173+
(v8i16 (REV16v16i8 (v8i16 V128:$Rn)))>;
5174+
def : Pat<(v2i32 (bswap (v2i32 V64:$Rn))),
5175+
(v2i32 (REV32v8i8 (v2i32 V64:$Rn)))>;
5176+
def : Pat<(v4i32 (bswap (v4i32 V128:$Rn))),
5177+
(v4i32 (REV32v16i8 (v4i32 V128:$Rn)))>;
5178+
def : Pat<(v2i64 (bswap (v2i64 V128:$Rn))),
5179+
(v2i64 (REV64v16i8 (v2i64 V128:$Rn)))>;
5180+
51695181
//===----------------------------------------------------------------------===//
51705182
// Advanced SIMD three vector instructions.
51715183
//===----------------------------------------------------------------------===//

‎llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp

Lines changed: 0 additions & 37 deletions
Original file line numberDiff line numberDiff line change
@@ -2567,43 +2567,6 @@ bool AArch64InstructionSelector::select(MachineInstr &I) {
25672567
return constrainSelectedInstRegOperands(*MovAddr, TII, TRI, RBI);
25682568
}
25692569

2570-
case TargetOpcode::G_BSWAP: {
2571-
// Handle vector types for G_BSWAP directly.
2572-
Register DstReg = I.getOperand(0).getReg();
2573-
LLT DstTy = MRI.getType(DstReg);
2574-
2575-
// We should only get vector types here; everything else is handled by the
2576-
// importer right now.
2577-
if (!DstTy.isVector() || DstTy.getSizeInBits() > 128) {
2578-
LLVM_DEBUG(dbgs() << "Dst type for G_BSWAP currently unsupported.\n");
2579-
return false;
2580-
}
2581-
2582-
// Only handle 4 and 2 element vectors for now.
2583-
// TODO: 16-bit elements.
2584-
unsigned NumElts = DstTy.getNumElements();
2585-
if (NumElts != 4 && NumElts != 2) {
2586-
LLVM_DEBUG(dbgs() << "Unsupported number of elements for G_BSWAP.\n");
2587-
return false;
2588-
}
2589-
2590-
// Choose the correct opcode for the supported types. Right now, that's
2591-
// v2s32, v4s32, and v2s64.
2592-
unsigned Opc = 0;
2593-
unsigned EltSize = DstTy.getElementType().getSizeInBits();
2594-
if (EltSize == 32)
2595-
Opc = (DstTy.getNumElements() == 2) ? AArch64::REV32v8i8
2596-
: AArch64::REV32v16i8;
2597-
else if (EltSize == 64)
2598-
Opc = AArch64::REV64v16i8;
2599-
2600-
// We should always get something by the time we get here...
2601-
assert(Opc != 0 && "Didn't get an opcode for G_BSWAP?");
2602-
2603-
I.setDesc(TII.get(Opc));
2604-
return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
2605-
}
2606-
26072570
case TargetOpcode::G_FCONSTANT:
26082571
case TargetOpcode::G_CONSTANT: {
26092572
const bool isFP = Opcode == TargetOpcode::G_FCONSTANT;

‎llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp

Lines changed: 7 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -118,9 +118,13 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
118118
.clampMaxNumElements(0, p0, 2);
119119

120120
getActionDefinitionsBuilder(G_BSWAP)
121-
.legalFor({s32, s64, v4s32, v2s32, v2s64})
122-
.widenScalarToNextPow2(0)
123-
.clampScalar(0, s32, s64);
121+
.legalFor({s32, s64, v4s16, v8s16, v2s32, v4s32, v2s64})
122+
.widenScalarOrEltToNextPow2(0, 16)
123+
.clampScalar(0, s32, s64)
124+
.clampNumElements(0, v4s16, v8s16)
125+
.clampNumElements(0, v2s32, v4s32)
126+
.clampNumElements(0, v2s64, v2s64)
127+
.moreElementsToNextPow2(0);
124128

125129
getActionDefinitionsBuilder({G_ADD, G_SUB, G_MUL, G_AND, G_OR, G_XOR})
126130
.legalFor({s32, s64, v2s32, v2s64, v4s32, v4s16, v8s16, v16s8, v8s8})

‎llvm/test/CodeGen/AArch64/GlobalISel/legalize-bswap.mir

Lines changed: 104 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -11,12 +11,13 @@ body: |
1111
1212
; CHECK-LABEL: name: bswap_s16
1313
; CHECK: liveins: $w0
14-
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
15-
; CHECK: [[BSWAP:%[0-9]+]]:_(s32) = G_BSWAP [[COPY]]
16-
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
17-
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BSWAP]], [[C]](s64)
18-
; CHECK: $w0 = COPY [[LSHR]](s32)
19-
; CHECK: RET_ReallyLR implicit $w0
14+
; CHECK-NEXT: {{ $}}
15+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
16+
; CHECK-NEXT: [[BSWAP:%[0-9]+]]:_(s32) = G_BSWAP [[COPY]]
17+
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
18+
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BSWAP]], [[C]](s64)
19+
; CHECK-NEXT: $w0 = COPY [[LSHR]](s32)
20+
; CHECK-NEXT: RET_ReallyLR implicit $w0
2021
%1:_(s32) = COPY $w0
2122
%0:_(s16) = G_TRUNC %1(s32)
2223
%2:_(s16) = G_BSWAP %0
@@ -32,10 +33,11 @@ body: |
3233
liveins: $w0
3334
; CHECK-LABEL: name: bswap_s32_legal
3435
; CHECK: liveins: $w0
35-
; CHECK: %copy:_(s32) = COPY $w0
36-
; CHECK: %bswap:_(s32) = G_BSWAP %copy
37-
; CHECK: $w0 = COPY %bswap(s32)
38-
; CHECK: RET_ReallyLR implicit $w0
36+
; CHECK-NEXT: {{ $}}
37+
; CHECK-NEXT: %copy:_(s32) = COPY $w0
38+
; CHECK-NEXT: %bswap:_(s32) = G_BSWAP %copy
39+
; CHECK-NEXT: $w0 = COPY %bswap(s32)
40+
; CHECK-NEXT: RET_ReallyLR implicit $w0
3941
%copy:_(s32) = COPY $w0
4042
%bswap:_(s32) = G_BSWAP %copy
4143
$w0 = COPY %bswap(s32)
@@ -49,27 +51,65 @@ body: |
4951
liveins: $x0
5052
; CHECK-LABEL: name: bswap_s64_legal
5153
; CHECK: liveins: $x0
52-
; CHECK: %copy:_(s64) = COPY $x0
53-
; CHECK: %bswap:_(s64) = G_BSWAP %copy
54-
; CHECK: $x0 = COPY %bswap(s64)
55-
; CHECK: RET_ReallyLR implicit $x0
54+
; CHECK-NEXT: {{ $}}
55+
; CHECK-NEXT: %copy:_(s64) = COPY $x0
56+
; CHECK-NEXT: %bswap:_(s64) = G_BSWAP %copy
57+
; CHECK-NEXT: $x0 = COPY %bswap(s64)
58+
; CHECK-NEXT: RET_ReallyLR implicit $x0
5659
%copy:_(s64) = COPY $x0
5760
%bswap:_(s64) = G_BSWAP %copy
5861
$x0 = COPY %bswap(s64)
5962
RET_ReallyLR implicit $x0
6063
...
6164
---
65+
name: bswap_v4s16_legal
66+
tracksRegLiveness: true
67+
body: |
68+
bb.0:
69+
liveins: $d0
70+
; CHECK-LABEL: name: bswap_v4s16_legal
71+
; CHECK: liveins: $d0
72+
; CHECK-NEXT: {{ $}}
73+
; CHECK-NEXT: %copy:_(<4 x s16>) = COPY $d0
74+
; CHECK-NEXT: %bswap:_(<4 x s16>) = G_BSWAP %copy
75+
; CHECK-NEXT: $d0 = COPY %bswap(<4 x s16>)
76+
; CHECK-NEXT: RET_ReallyLR implicit $d0
77+
%copy:_(<4 x s16>) = COPY $d0
78+
%bswap:_(<4 x s16>) = G_BSWAP %copy
79+
$d0 = COPY %bswap(<4 x s16>)
80+
RET_ReallyLR implicit $d0
81+
...
82+
---
83+
name: bswap_v8s16_legal
84+
tracksRegLiveness: true
85+
body: |
86+
bb.0:
87+
liveins: $q0
88+
; CHECK-LABEL: name: bswap_v8s16_legal
89+
; CHECK: liveins: $q0
90+
; CHECK-NEXT: {{ $}}
91+
; CHECK-NEXT: %copy:_(<8 x s16>) = COPY $q0
92+
; CHECK-NEXT: %bswap:_(<8 x s16>) = G_BSWAP %copy
93+
; CHECK-NEXT: $q0 = COPY %bswap(<8 x s16>)
94+
; CHECK-NEXT: RET_ReallyLR implicit $q0
95+
%copy:_(<8 x s16>) = COPY $q0
96+
%bswap:_(<8 x s16>) = G_BSWAP %copy
97+
$q0 = COPY %bswap(<8 x s16>)
98+
RET_ReallyLR implicit $q0
99+
...
100+
---
62101
name: bswap_v4s32_legal
63102
tracksRegLiveness: true
64103
body: |
65104
bb.0:
66105
liveins: $q0
67106
; CHECK-LABEL: name: bswap_v4s32_legal
68107
; CHECK: liveins: $q0
69-
; CHECK: %copy:_(<4 x s32>) = COPY $q0
70-
; CHECK: %bswap:_(<4 x s32>) = G_BSWAP %copy
71-
; CHECK: $q0 = COPY %bswap(<4 x s32>)
72-
; CHECK: RET_ReallyLR implicit $q0
108+
; CHECK-NEXT: {{ $}}
109+
; CHECK-NEXT: %copy:_(<4 x s32>) = COPY $q0
110+
; CHECK-NEXT: %bswap:_(<4 x s32>) = G_BSWAP %copy
111+
; CHECK-NEXT: $q0 = COPY %bswap(<4 x s32>)
112+
; CHECK-NEXT: RET_ReallyLR implicit $q0
73113
%copy:_(<4 x s32>) = COPY $q0
74114
%bswap:_(<4 x s32>) = G_BSWAP %copy
75115
$q0 = COPY %bswap(<4 x s32>)
@@ -83,10 +123,11 @@ body: |
83123
liveins: $d0
84124
; CHECK-LABEL: name: bswap_v2s32_legal
85125
; CHECK: liveins: $d0
86-
; CHECK: %copy:_(<2 x s32>) = COPY $d0
87-
; CHECK: %bswap:_(<2 x s32>) = G_BSWAP %copy
88-
; CHECK: $d0 = COPY %bswap(<2 x s32>)
89-
; CHECK: RET_ReallyLR implicit $d0
126+
; CHECK-NEXT: {{ $}}
127+
; CHECK-NEXT: %copy:_(<2 x s32>) = COPY $d0
128+
; CHECK-NEXT: %bswap:_(<2 x s32>) = G_BSWAP %copy
129+
; CHECK-NEXT: $d0 = COPY %bswap(<2 x s32>)
130+
; CHECK-NEXT: RET_ReallyLR implicit $d0
90131
%copy:_(<2 x s32>) = COPY $d0
91132
%bswap:_(<2 x s32>) = G_BSWAP %copy
92133
$d0 = COPY %bswap(<2 x s32>)
@@ -100,10 +141,11 @@ body: |
100141
liveins: $q0
101142
; CHECK-LABEL: name: bswap_v2s64_legal
102143
; CHECK: liveins: $q0
103-
; CHECK: %copy:_(<2 x s64>) = COPY $q0
104-
; CHECK: %bswap:_(<2 x s64>) = G_BSWAP %copy
105-
; CHECK: $q0 = COPY %bswap(<2 x s64>)
106-
; CHECK: RET_ReallyLR implicit $q0
144+
; CHECK-NEXT: {{ $}}
145+
; CHECK-NEXT: %copy:_(<2 x s64>) = COPY $q0
146+
; CHECK-NEXT: %bswap:_(<2 x s64>) = G_BSWAP %copy
147+
; CHECK-NEXT: $q0 = COPY %bswap(<2 x s64>)
148+
; CHECK-NEXT: RET_ReallyLR implicit $q0
107149
%copy:_(<2 x s64>) = COPY $q0
108150
%bswap:_(<2 x s64>) = G_BSWAP %copy
109151
$q0 = COPY %bswap(<2 x s64>)
@@ -134,3 +176,39 @@ body: |
134176
$x0 = COPY %trunc(s64)
135177
RET_ReallyLR implicit $x0
136178
...
179+
---
180+
name: bswap_v2s48
181+
tracksRegLiveness: true
182+
body: |
183+
bb.0:
184+
liveins: $q0, $x8
185+
; CHECK-LABEL: name: bswap_v2s48
186+
; CHECK: liveins: $q0, $x8
187+
; CHECK-NEXT: {{ $}}
188+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x8
189+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q0
190+
; CHECK-NEXT: [[BSWAP:%[0-9]+]]:_(<2 x s64>) = G_BSWAP [[COPY1]]
191+
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
192+
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
193+
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(<2 x s64>) = G_LSHR [[BSWAP]], [[BUILD_VECTOR]](<2 x s64>)
194+
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[LSHR]](<2 x s64>)
195+
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
196+
; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[C1]](s64)
197+
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
198+
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C2]](s64)
199+
; CHECK-NEXT: G_STORE [[UV]](s64), [[COPY]](p0) :: (store (s32), align 16)
200+
; CHECK-NEXT: G_STORE [[LSHR1]](s64), [[PTR_ADD]](p0) :: (store (s16) into unknown-address + 4, align 4)
201+
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 6
202+
; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C3]](s64)
203+
; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[UV1]], [[C1]](s64)
204+
; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD1]], [[C2]](s64)
205+
; CHECK-NEXT: G_STORE [[UV1]](s64), [[PTR_ADD1]](p0) :: (store (s32) into unknown-address + 6, align 2)
206+
; CHECK-NEXT: G_STORE [[LSHR2]](s64), [[PTR_ADD2]](p0) :: (store (s16) into unknown-address + 10)
207+
; CHECK-NEXT: RET_ReallyLR
208+
%1:_(p0) = COPY $x8
209+
%2:_(<2 x s64>) = COPY $q0
210+
%0:_(<2 x s48>) = G_TRUNC %2:_(<2 x s64>)
211+
%bswap:_(<2 x s48>) = G_BSWAP %0
212+
G_STORE %bswap:_(<2 x s48>), %1:_(p0) :: (store (<2 x s48>), align 16)
213+
RET_ReallyLR
214+
...

‎llvm/test/CodeGen/AArch64/GlobalISel/select-bswap.mir

Lines changed: 72 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -16,9 +16,11 @@ body: |
1616
liveins: $w0
1717
1818
; CHECK-LABEL: name: bswap_s32
19-
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
20-
; CHECK: [[REVWr:%[0-9]+]]:gpr32 = REVWr [[COPY]]
21-
; CHECK: $w0 = COPY [[REVWr]]
19+
; CHECK: liveins: $w0
20+
; CHECK-NEXT: {{ $}}
21+
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
22+
; CHECK-NEXT: [[REVWr:%[0-9]+]]:gpr32 = REVWr [[COPY]]
23+
; CHECK-NEXT: $w0 = COPY [[REVWr]]
2224
%0(s32) = COPY $w0
2325
%1(s32) = G_BSWAP %0
2426
$w0 = COPY %1
@@ -38,13 +40,62 @@ body: |
3840
liveins: $x0
3941
4042
; CHECK-LABEL: name: bswap_s64
41-
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
42-
; CHECK: [[REVXr:%[0-9]+]]:gpr64 = REVXr [[COPY]]
43-
; CHECK: $x0 = COPY [[REVXr]]
43+
; CHECK: liveins: $x0
44+
; CHECK-NEXT: {{ $}}
45+
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
46+
; CHECK-NEXT: [[REVXr:%[0-9]+]]:gpr64 = REVXr [[COPY]]
47+
; CHECK-NEXT: $x0 = COPY [[REVXr]]
4448
%0(s64) = COPY $x0
4549
%1(s64) = G_BSWAP %0
4650
$x0 = COPY %1
4751
52+
...
53+
---
54+
name: bswap_v4s16
55+
alignment: 4
56+
legalized: true
57+
regBankSelected: true
58+
tracksRegLiveness: true
59+
machineFunctionInfo: {}
60+
body: |
61+
bb.0:
62+
liveins: $d0
63+
64+
; CHECK-LABEL: name: bswap_v4s16
65+
; CHECK: liveins: $d0
66+
; CHECK-NEXT: {{ $}}
67+
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
68+
; CHECK-NEXT: [[REV16v8i8_:%[0-9]+]]:fpr64 = REV16v8i8 [[COPY]]
69+
; CHECK-NEXT: $d0 = COPY [[REV16v8i8_]]
70+
; CHECK-NEXT: RET_ReallyLR implicit $d0
71+
%0:fpr(<4 x s16>) = COPY $d0
72+
%1:fpr(<4 x s16>) = G_BSWAP %0
73+
$d0 = COPY %1(<4 x s16>)
74+
RET_ReallyLR implicit $d0
75+
76+
...
77+
---
78+
name: bswap_v8s16
79+
alignment: 4
80+
legalized: true
81+
regBankSelected: true
82+
tracksRegLiveness: true
83+
machineFunctionInfo: {}
84+
body: |
85+
bb.0:
86+
liveins: $q0
87+
; CHECK-LABEL: name: bswap_v8s16
88+
; CHECK: liveins: $q0
89+
; CHECK-NEXT: {{ $}}
90+
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
91+
; CHECK-NEXT: [[REV16v16i8_:%[0-9]+]]:fpr128 = REV16v16i8 [[COPY]]
92+
; CHECK-NEXT: $q0 = COPY [[REV16v16i8_]]
93+
; CHECK-NEXT: RET_ReallyLR implicit $q0
94+
%0:fpr(<8 x s16>) = COPY $q0
95+
%1:fpr(<8 x s16>) = G_BSWAP %0
96+
$q0 = COPY %1(<8 x s16>)
97+
RET_ReallyLR implicit $q0
98+
4899
...
49100
---
50101
name: bswap_v4s32
@@ -59,10 +110,11 @@ body: |
59110
60111
; CHECK-LABEL: name: bswap_v4s32
61112
; CHECK: liveins: $q0
62-
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
63-
; CHECK: [[REV32v16i8_:%[0-9]+]]:fpr128 = REV32v16i8 [[COPY]]
64-
; CHECK: $q0 = COPY [[REV32v16i8_]]
65-
; CHECK: RET_ReallyLR implicit $q0
113+
; CHECK-NEXT: {{ $}}
114+
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
115+
; CHECK-NEXT: [[REV32v16i8_:%[0-9]+]]:fpr128 = REV32v16i8 [[COPY]]
116+
; CHECK-NEXT: $q0 = COPY [[REV32v16i8_]]
117+
; CHECK-NEXT: RET_ReallyLR implicit $q0
66118
%0:fpr(<4 x s32>) = COPY $q0
67119
%1:fpr(<4 x s32>) = G_BSWAP %0
68120
$q0 = COPY %1(<4 x s32>)
@@ -82,10 +134,11 @@ body: |
82134
83135
; CHECK-LABEL: name: bswap_v2s32
84136
; CHECK: liveins: $d0
85-
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
86-
; CHECK: [[REV32v8i8_:%[0-9]+]]:fpr64 = REV32v8i8 [[COPY]]
87-
; CHECK: $d0 = COPY [[REV32v8i8_]]
88-
; CHECK: RET_ReallyLR implicit $d0
137+
; CHECK-NEXT: {{ $}}
138+
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
139+
; CHECK-NEXT: [[REV32v8i8_:%[0-9]+]]:fpr64 = REV32v8i8 [[COPY]]
140+
; CHECK-NEXT: $d0 = COPY [[REV32v8i8_]]
141+
; CHECK-NEXT: RET_ReallyLR implicit $d0
89142
%0:fpr(<2 x s32>) = COPY $d0
90143
%1:fpr(<2 x s32>) = G_BSWAP %0
91144
$d0 = COPY %1(<2 x s32>)
@@ -105,10 +158,11 @@ body: |
105158
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; CHECK-LABEL: name: bswap_v2s64
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; CHECK: liveins: $q0
108-
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
109-
; CHECK: [[REV64v16i8_:%[0-9]+]]:fpr128 = REV64v16i8 [[COPY]]
110-
; CHECK: $q0 = COPY [[REV64v16i8_]]
111-
; CHECK: RET_ReallyLR implicit $q0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
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; CHECK-NEXT: [[REV64v16i8_:%[0-9]+]]:fpr128 = REV64v16i8 [[COPY]]
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; CHECK-NEXT: $q0 = COPY [[REV64v16i8_]]
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; CHECK-NEXT: RET_ReallyLR implicit $q0
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%0:fpr(<2 x s64>) = COPY $q0
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%1:fpr(<2 x s64>) = G_BSWAP %0
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$q0 = COPY %1(<2 x s64>)

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