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fix conflict
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+40
-119
lines changed

5 files changed

+40
-119
lines changed

llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp

Lines changed: 16 additions & 57 deletions
Original file line numberDiff line numberDiff line change
@@ -1072,11 +1072,11 @@ static InstructionsState getSameOpcode(ArrayRef<Value *> VL,
10721072
if (!isTriviallyVectorizable(BaseID) && BaseMappings.empty())
10731073
return InstructionsState::invalid();
10741074
}
1075-
<<<<<<< HEAD
1075+
bool AnyPoison = InstCnt != VL.size();
10761076
// Currently, this is only used for binary ops.
10771077
// TODO: support all instructions
10781078
SmallVector<InterchangeableInstruction> InterchangeableOpcode =
1079-
getInterchangeableInstruction(cast<Instruction>(VL[BaseIndex]));
1079+
getInterchangeableInstruction(cast<Instruction>(V));
10801080
SmallVector<InterchangeableInstruction> AlternateInterchangeableOpcode;
10811081
auto UpdateInterchangeableOpcode =
10821082
[](SmallVector<InterchangeableInstruction> &LHS,
@@ -1089,9 +1089,6 @@ static InstructionsState getSameOpcode(ArrayRef<Value *> VL,
10891089
LHS.swap(NewInterchangeableOpcode);
10901090
return true;
10911091
};
1092-
=======
1093-
bool AnyPoison = InstCnt != VL.size();
1094-
>>>>>>> upstream/main
10951092
for (int Cnt = 0, E = VL.size(); Cnt < E; Cnt++) {
10961093
auto *I = dyn_cast<Instruction>(VL[Cnt]);
10971094
if (!I)
@@ -1123,7 +1120,7 @@ static InstructionsState getSameOpcode(ArrayRef<Value *> VL,
11231120
}),
11241121
ThisInterchangeableOpcode.end());
11251122
if (InterchangeableOpcode.empty() || ThisInterchangeableOpcode.empty())
1126-
return InstructionsState(VL[BaseIndex], nullptr, nullptr);
1123+
return InstructionsState::invalid();
11271124
AlternateInterchangeableOpcode.swap(ThisInterchangeableOpcode);
11281125
continue;
11291126
}
@@ -1230,7 +1227,6 @@ static InstructionsState getSameOpcode(ArrayRef<Value *> VL,
12301227
return InstructionsState::invalid();
12311228
}
12321229

1233-
<<<<<<< HEAD
12341230
if (IsBinOp) {
12351231
auto FindOp = [&](ArrayRef<InterchangeableInstruction> CandidateOp) {
12361232
for (Value *V : VL)
@@ -1244,12 +1240,9 @@ static InstructionsState getSameOpcode(ArrayRef<Value *> VL,
12441240
Instruction *AltOp = AlternateInterchangeableOpcode.empty()
12451241
? MainOp
12461242
: FindOp(AlternateInterchangeableOpcode);
1247-
return InstructionsState(VL[BaseIndex], MainOp, AltOp);
1243+
return InstructionsState(MainOp, AltOp);
12481244
}
1249-
return InstructionsState(VL[BaseIndex], cast<Instruction>(VL[BaseIndex]),
1250-
=======
12511245
return InstructionsState(cast<Instruction>(V),
1252-
>>>>>>> upstream/main
12531246
cast<Instruction>(VL[AltIndex]));
12541247
}
12551248

@@ -2593,11 +2586,18 @@ class BoUpSLP {
25932586
InstructionsState S = getSameOpcode(VL, TLI);
25942587
for (unsigned OpIdx : seq<unsigned>(NumOperands))
25952588
OpsVec[OpIdx].resize(NumLanes);
2596-
<<<<<<< HEAD
2597-
for (auto [I, V] : enumerate(VL)) {
2598-
assert(isa<Instruction>(V) && "Expected instruction");
2589+
for (auto [Lane, V] : enumerate(VL)) {
2590+
assert((isa<Instruction>(V) || isa<PoisonValue>(V)) &&
2591+
"Expected instruction or poison value");
2592+
if (isa<PoisonValue>(V)) {
2593+
for (unsigned OpIdx : seq<unsigned>(NumOperands))
2594+
OpsVec[OpIdx][Lane] = {
2595+
PoisonValue::get(VL0->getOperand(OpIdx)->getType()), true,
2596+
false};
2597+
continue;
2598+
}
25992599
auto [SelectedOp, Ops] = getInterchangeableInstruction(
2600-
cast<Instruction>(V), S.MainOp, S.AltOp);
2600+
cast<Instruction>(V), S.getMainOp(), S.getAltOp());
26012601
// Our tree has just 3 nodes: the root and two operands.
26022602
// It is therefore trivial to get the APO. We only need to check the
26032603
// opcode of V and whether the operand at OpIdx is the LHS or RHS
@@ -2610,30 +2610,8 @@ class BoUpSLP {
26102610
// tell the inverse operations by checking commutativity.
26112611
bool IsInverseOperation = !isCommutative(cast<Instruction>(SelectedOp));
26122612
for (unsigned OpIdx : seq<unsigned>(NumOperands)) {
2613-
=======
2614-
for (unsigned Lane = 0; Lane != NumLanes; ++Lane) {
2615-
assert((isa<Instruction>(VL[Lane]) || isa<PoisonValue>(VL[Lane])) &&
2616-
"Expected instruction or poison value");
2617-
// Our tree has just 3 nodes: the root and two operands.
2618-
// It is therefore trivial to get the APO. We only need to check the
2619-
// opcode of VL[Lane] and whether the operand at OpIdx is the LHS or
2620-
// RHS operand. The LHS operand of both add and sub is never attached
2621-
// to an inversese operation in the linearized form, therefore its APO
2622-
// is false. The RHS is true only if VL[Lane] is an inverse operation.
2623-
2624-
// Since operand reordering is performed on groups of commutative
2625-
// operations or alternating sequences (e.g., +, -), we can safely
2626-
// tell the inverse operations by checking commutativity.
2627-
if (isa<PoisonValue>(VL[Lane])) {
2628-
OpsVec[OpIdx][Lane] = {
2629-
PoisonValue::get(VL0->getOperand(OpIdx)->getType()), true,
2630-
false};
2631-
continue;
2632-
}
2633-
bool IsInverseOperation = !isCommutative(cast<Instruction>(VL[Lane]));
2634-
>>>>>>> upstream/main
26352613
bool APO = (OpIdx == 0) ? false : IsInverseOperation;
2636-
OpsVec[OpIdx][I] = {Ops[OpIdx], APO, false};
2614+
OpsVec[OpIdx][Lane] = {Ops[OpIdx], APO, false};
26372615
}
26382616
}
26392617
}
@@ -3534,32 +3512,13 @@ class BoUpSLP {
35343512
copy(OpVL, Operands[OpIdx].begin());
35353513
}
35363514

3537-
<<<<<<< HEAD
3538-
/// Set the operands of this bundle in their original order.
3539-
void setOperandsInOrder() {
3540-
assert(Operands.empty() && "Already initialized?");
3541-
auto *I0 = cast<Instruction>(Scalars[0]);
3542-
Operands.resize(I0->getNumOperands());
3543-
unsigned NumLanes = Scalars.size();
3544-
unsigned NumOperands = I0->getNumOperands();
3545-
for (unsigned OpIdx : seq<unsigned>(NumOperands))
3546-
Operands[OpIdx].resize(NumLanes);
3547-
for (auto [I, V] : enumerate(Scalars)) {
3548-
auto [SelectedOp, Ops] =
3549-
getInterchangeableInstruction(cast<Instruction>(V), MainOp, AltOp);
3550-
assert(Ops.size() == NumOperands && "Expected same number of operands");
3551-
for (auto [J, Op] : enumerate(Ops))
3552-
Operands[J][I] = Op;
3553-
}
3554-
=======
35553515
/// Set this bundle's operand from Scalars.
35563516
void setOperand(const BoUpSLP &R, bool RequireReorder = false) {
35573517
VLOperands Ops(Scalars, MainOp, R);
35583518
if (RequireReorder)
35593519
Ops.reorder();
35603520
for (unsigned I : seq<unsigned>(MainOp->getNumOperands()))
35613521
setOperand(I, Ops.getVL(I));
3562-
>>>>>>> upstream/main
35633522
}
35643523

35653524
/// Reorders operands of the node to the given mask \p Mask.

llvm/test/Transforms/SLPVectorizer/RISCV/reversed-strided-node-with-external-ptr.ll

Lines changed: 6 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -12,18 +12,13 @@ define void @test(ptr %a, i64 %0) {
1212
; CHECK: [[BB]]:
1313
; CHECK-NEXT: [[TMP5:%.*]] = or disjoint <2 x i64> [[TMP3]], <i64 1, i64 0>
1414
; CHECK-NEXT: [[TMP6:%.*]] = getelementptr double, <2 x ptr> [[TMP2]], <2 x i64> [[TMP5]]
15-
<<<<<<< HEAD
16-
; CHECK-NEXT: [[ARRAYIDX17_I28_1:%.*]] = extractelement <2 x ptr> [[TMP6]], i32 0
17-
; CHECK-NEXT: [[TMP7:%.*]] = call <2 x double> @llvm.masked.gather.v2f64.v2p0(<2 x ptr> [[TMP6]], i32 8, <2 x i1> <i1 true, i1 true>, <2 x double> poison)
18-
=======
19-
; CHECK-NEXT: [[ARRAYIDX17_I28_1:%.*]] = getelementptr double, ptr [[A]], i64 [[TMP3]]
20-
; CHECK-NEXT: [[TMP7:%.*]] = call <2 x double> @llvm.masked.gather.v2f64.v2p0(<2 x ptr> [[TMP6]], i32 8, <2 x i1> splat (i1 true), <2 x double> poison)
21-
>>>>>>> upstream/main
22-
; CHECK-NEXT: [[TMP8:%.*]] = load <2 x double>, ptr [[A]], align 8
23-
; CHECK-NEXT: [[TMP9:%.*]] = load <2 x double>, ptr [[A]], align 8
24-
; CHECK-NEXT: [[TMP10:%.*]] = fsub <2 x double> [[TMP8]], [[TMP9]]
15+
; CHECK-NEXT: [[TMP8:%.*]] = extractelement <2 x ptr> [[TMP6]], i32 0
16+
; CHECK-NEXT: [[TMP9:%.*]] = call <2 x double> @llvm.masked.gather.v2f64.v2p0(<2 x ptr> [[TMP6]], i32 8, <2 x i1> splat (i1 true), <2 x double> poison)
17+
; CHECK-NEXT: [[TMP7:%.*]] = load <2 x double>, ptr [[A]], align 8
18+
; CHECK-NEXT: [[TMP10:%.*]] = load <2 x double>, ptr [[A]], align 8
2519
; CHECK-NEXT: [[TMP11:%.*]] = fsub <2 x double> [[TMP7]], [[TMP10]]
26-
; CHECK-NEXT: call void @llvm.experimental.vp.strided.store.v2f64.p0.i64(<2 x double> [[TMP11]], ptr align 8 [[ARRAYIDX17_I28_1]], i64 -8, <2 x i1> splat (i1 true), i32 2)
20+
; CHECK-NEXT: [[TMP12:%.*]] = fsub <2 x double> [[TMP9]], [[TMP11]]
21+
; CHECK-NEXT: call void @llvm.experimental.vp.strided.store.v2f64.p0.i64(<2 x double> [[TMP12]], ptr align 8 [[TMP8]], i64 -8, <2 x i1> splat (i1 true), i32 2)
2722
; CHECK-NEXT: br label %[[BB]]
2823
;
2924
entry:

llvm/test/Transforms/SLPVectorizer/X86/barriercall.ll

Lines changed: 2 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -10,15 +10,8 @@ define i32 @foo(ptr nocapture %A, i32 %n) {
1010
; CHECK-NEXT: [[CALL:%.*]] = tail call i32 (...) @bar()
1111
; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> poison, i32 [[N:%.*]], i32 0
1212
; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <4 x i32> [[TMP0]], <4 x i32> poison, <4 x i32> zeroinitializer
13-
<<<<<<< HEAD
14-
; CHECK-NEXT: [[TMP3:%.*]] = mul <4 x i32> [[SHUFFLE]], <i32 5, i32 9, i32 8, i32 10>
15-
; CHECK-NEXT: [[TMP4:%.*]] = add nsw <4 x i32> [[TMP3]], <i32 9, i32 9, i32 9, i32 9>
16-
=======
17-
; CHECK-NEXT: [[TMP1:%.*]] = mul nsw <4 x i32> [[SHUFFLE]], <i32 5, i32 9, i32 3, i32 10>
18-
; CHECK-NEXT: [[TMP2:%.*]] = shl <4 x i32> [[SHUFFLE]], <i32 5, i32 9, i32 3, i32 10>
19-
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> [[TMP2]], <4 x i32> <i32 0, i32 1, i32 6, i32 3>
20-
; CHECK-NEXT: [[TMP4:%.*]] = add nsw <4 x i32> [[TMP3]], splat (i32 9)
21-
>>>>>>> upstream/main
13+
; CHECK-NEXT: [[TMP2:%.*]] = mul <4 x i32> [[SHUFFLE]], <i32 5, i32 9, i32 8, i32 10>
14+
; CHECK-NEXT: [[TMP4:%.*]] = add nsw <4 x i32> [[TMP2]], splat (i32 9)
2215
; CHECK-NEXT: store <4 x i32> [[TMP4]], ptr [[A:%.*]], align 4
2316
; CHECK-NEXT: ret i32 undef
2417
;

llvm/test/Transforms/SLPVectorizer/X86/extract-scalar-from-undef.ll

Lines changed: 12 additions & 31 deletions
Original file line numberDiff line numberDiff line change
@@ -4,38 +4,19 @@
44
define i64 @foo(i32 %tmp7) {
55
; CHECK-LABEL: @foo(
66
; CHECK-NEXT: bb:
7-
<<<<<<< HEAD
8-
; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i32> <i32 poison, i32 0>, i32 [[TMP7:%.*]], i32 0
9-
; CHECK-NEXT: [[TMP1:%.*]] = sub <2 x i32> [[TMP0]], zeroinitializer
7+
; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> <i32 0, i32 0, i32 poison, i32 0>, i32 [[TMP7:%.*]], i32 2
8+
; CHECK-NEXT: [[TMP1:%.*]] = sub <4 x i32> [[TMP0]], zeroinitializer
109
; CHECK-NEXT: [[TMP2:%.*]] = call <8 x i32> @llvm.vector.insert.v8i32.v2i32(<8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 poison, i32 poison, i32 undef, i32 0>, <2 x i32> <i32 undef, i32 0>, i64 4)
11-
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> poison, <8 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
12-
; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <8 x i32> [[TMP3]], <8 x i32> <i32 poison, i32 poison, i32 undef, i32 poison, i32 poison, i32 undef, i32 poison, i32 undef>, <8 x i32> <i32 poison, i32 poison, i32 10, i32 0, i32 1, i32 13, i32 poison, i32 15>
13-
; CHECK-NEXT: [[TMP5:%.*]] = insertelement <8 x i32> [[TMP4]], i32 undef, i32 6
14-
; CHECK-NEXT: [[TMP6:%.*]] = call <8 x i32> @llvm.vector.insert.v8i32.v2i32(<8 x i32> [[TMP5]], <2 x i32> zeroinitializer, i64 0)
15-
; CHECK-NEXT: [[TMP7:%.*]] = add nsw <8 x i32> [[TMP2]], [[TMP6]]
16-
; CHECK-NEXT: [[TMP8:%.*]] = sub nsw <8 x i32> [[TMP2]], [[TMP6]]
17-
; CHECK-NEXT: [[TMP9:%.*]] = shufflevector <8 x i32> [[TMP7]], <8 x i32> [[TMP8]], <8 x i32> <i32 0, i32 9, i32 10, i32 11, i32 4, i32 5, i32 14, i32 15>
18-
; CHECK-NEXT: [[TMP10:%.*]] = add <8 x i32> zeroinitializer, [[TMP9]]
19-
; CHECK-NEXT: [[TMP11:%.*]] = xor <8 x i32> [[TMP10]], zeroinitializer
20-
; CHECK-NEXT: [[TMP12:%.*]] = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> [[TMP11]])
21-
; CHECK-NEXT: [[OP_RDX:%.*]] = add i32 [[TMP12]], 0
22-
=======
23-
; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> <i32 0, i32 0, i32 poison, i32 0>, i32 [[TMP5:%.*]], i32 2
24-
; CHECK-NEXT: [[TMP3:%.*]] = sub <4 x i32> [[TMP2]], zeroinitializer
25-
; CHECK-NEXT: [[TMP24:%.*]] = sub i32 undef, 0
26-
; CHECK-NEXT: [[TMP0:%.*]] = insertelement <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 poison, i32 poison, i32 undef, i32 0>, i32 [[TMP24]], i32 4
27-
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <8 x i32> [[TMP0]], i32 0, i32 5
28-
; CHECK-NEXT: [[TMP11:%.*]] = insertelement <8 x i32> <i32 poison, i32 poison, i32 undef, i32 poison, i32 poison, i32 undef, i32 poison, i32 undef>, i32 [[TMP24]], i32 6
29-
; CHECK-NEXT: [[TMP12:%.*]] = call <8 x i32> @llvm.vector.insert.v8i32.v4i32(<8 x i32> poison, <4 x i32> [[TMP3]], i64 0)
30-
; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <8 x i32> [[TMP12]], <8 x i32> [[TMP11]], <8 x i32> <i32 0, i32 1, i32 poison, i32 2, i32 3, i32 poison, i32 14, i32 poison>
31-
; CHECK-NEXT: [[TMP5:%.*]] = add nsw <8 x i32> [[TMP1]], [[TMP4]]
32-
; CHECK-NEXT: [[TMP6:%.*]] = sub nsw <8 x i32> [[TMP1]], [[TMP4]]
33-
; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <8 x i32> [[TMP5]], <8 x i32> [[TMP6]], <8 x i32> <i32 0, i32 9, i32 10, i32 11, i32 4, i32 5, i32 14, i32 15>
34-
; CHECK-NEXT: [[TMP8:%.*]] = add <8 x i32> zeroinitializer, [[TMP7]]
35-
; CHECK-NEXT: [[TMP9:%.*]] = xor <8 x i32> [[TMP8]], zeroinitializer
36-
; CHECK-NEXT: [[TMP10:%.*]] = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> [[TMP9]])
37-
; CHECK-NEXT: [[OP_RDX:%.*]] = add i32 [[TMP10]], 0
38-
>>>>>>> upstream/main
10+
; CHECK-NEXT: [[TMP3:%.*]] = insertelement <8 x i32> <i32 poison, i32 poison, i32 undef, i32 poison, i32 poison, i32 undef, i32 poison, i32 undef>, i32 undef, i32 6
11+
; CHECK-NEXT: [[TMP4:%.*]] = call <8 x i32> @llvm.vector.insert.v8i32.v4i32(<8 x i32> poison, <4 x i32> [[TMP1]], i64 0)
12+
; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <8 x i32> [[TMP4]], <8 x i32> [[TMP3]], <8 x i32> <i32 0, i32 1, i32 poison, i32 2, i32 3, i32 poison, i32 14, i32 poison>
13+
; CHECK-NEXT: [[TMP6:%.*]] = add nsw <8 x i32> [[TMP2]], [[TMP5]]
14+
; CHECK-NEXT: [[TMP7:%.*]] = sub nsw <8 x i32> [[TMP2]], [[TMP5]]
15+
; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <8 x i32> [[TMP6]], <8 x i32> [[TMP7]], <8 x i32> <i32 0, i32 9, i32 10, i32 11, i32 4, i32 5, i32 14, i32 15>
16+
; CHECK-NEXT: [[TMP9:%.*]] = add <8 x i32> zeroinitializer, [[TMP8]]
17+
; CHECK-NEXT: [[TMP10:%.*]] = xor <8 x i32> [[TMP9]], zeroinitializer
18+
; CHECK-NEXT: [[TMP11:%.*]] = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> [[TMP10]])
19+
; CHECK-NEXT: [[OP_RDX:%.*]] = add i32 [[TMP11]], 0
3920
; CHECK-NEXT: [[TMP64:%.*]] = zext i32 [[OP_RDX]] to i64
4021
; CHECK-NEXT: ret i64 [[TMP64]]
4122
;

llvm/test/Transforms/SLPVectorizer/X86/extractcost.ll

Lines changed: 4 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -9,17 +9,10 @@ define i32 @foo(ptr nocapture %A, i32 %n, i32 %m) {
99
; CHECK-NEXT: entry:
1010
; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> poison, i32 [[N:%.*]], i32 0
1111
; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <4 x i32> [[TMP0]], <4 x i32> poison, <4 x i32> zeroinitializer
12-
<<<<<<< HEAD
13-
; CHECK-NEXT: [[TMP3:%.*]] = mul <4 x i32> [[SHUFFLE]], <i32 5, i32 9, i32 8, i32 10>
14-
; CHECK-NEXT: [[TMP4:%.*]] = add nsw <4 x i32> [[TMP3]], <i32 9, i32 9, i32 9, i32 9>
15-
=======
16-
; CHECK-NEXT: [[TMP1:%.*]] = mul nsw <4 x i32> [[SHUFFLE]], <i32 5, i32 9, i32 3, i32 10>
17-
; CHECK-NEXT: [[TMP2:%.*]] = shl <4 x i32> [[SHUFFLE]], <i32 5, i32 9, i32 3, i32 10>
18-
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> [[TMP2]], <4 x i32> <i32 0, i32 1, i32 6, i32 3>
19-
; CHECK-NEXT: [[TMP4:%.*]] = add nsw <4 x i32> [[TMP3]], splat (i32 9)
20-
>>>>>>> upstream/main
21-
; CHECK-NEXT: store <4 x i32> [[TMP4]], ptr [[A:%.*]], align 4
22-
; CHECK-NEXT: [[TMP6:%.*]] = extractelement <4 x i32> [[TMP4]], i32 0
12+
; CHECK-NEXT: [[TMP2:%.*]] = mul <4 x i32> [[SHUFFLE]], <i32 5, i32 9, i32 8, i32 10>
13+
; CHECK-NEXT: [[TMP3:%.*]] = add nsw <4 x i32> [[TMP2]], splat (i32 9)
14+
; CHECK-NEXT: store <4 x i32> [[TMP3]], ptr [[A:%.*]], align 4
15+
; CHECK-NEXT: [[TMP6:%.*]] = extractelement <4 x i32> [[TMP3]], i32 0
2316
; CHECK-NEXT: [[EXTERNALUSE1:%.*]] = add nsw i32 [[TMP6]], [[M:%.*]]
2417
; CHECK-NEXT: [[EXTERNALUSE2:%.*]] = mul nsw i32 [[TMP6]], [[M]]
2518
; CHECK-NEXT: [[ADD10:%.*]] = add nsw i32 [[EXTERNALUSE1]], [[EXTERNALUSE2]]

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