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[LV] Don't skip instrs with side-effects in reg pressure computation. (#126415)
calculateRegisterUsage adds end points for each user of an instruction to Ends and ignores instructions not added to it, i.e. instructions with no users. This means things like stores aren't included, which in turn means values that are only used in stores are also not included for consideration. This means we underestimate the register usage in cases where the only users are things like stores. Update the code to don't skip instructions without users (i.e. not in Ends) if they have side-effects. PR: #126415
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5 files changed

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lines changed

‎llvm/lib/Transforms/Vectorize/LoopVectorize.cpp

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -5270,8 +5270,9 @@ LoopVectorizationCostModel::calculateRegisterUsage(ArrayRef<ElementCount> VFs) {
52705270
for (Instruction *ToRemove : List)
52715271
OpenIntervals.erase(ToRemove);
52725272

5273-
// Ignore instructions that are never used within the loop.
5274-
if (!Ends.count(I))
5273+
// Ignore instructions that are never used within the loop and do not have
5274+
// side-effects.
5275+
if (!Ends.count(I) && !I->mayHaveSideEffects())
52755276
continue;
52765277

52775278
// Skip ignored values.

‎llvm/test/Transforms/LoopVectorize/AArch64/reg-usage.ll

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -15,8 +15,9 @@
1515
define void @get_invariant_reg_usage(ptr %z) {
1616
; CHECK-LABEL: LV: Checking a loop in 'get_invariant_reg_usage'
1717
; CHECK: LV(REG): VF = vscale x 16
18-
; CHECK-NEXT: LV(REG): Found max usage: 1 item
18+
; CHECK-NEXT: LV(REG): Found max usage: 2 item
1919
; CHECK-NEXT: LV(REG): RegisterClass: Generic::ScalarRC, 3 registers
20+
; CHECK-NEXT: LV(REG): RegisterClass: Generic::VectorRC, 1 registers
2021
; CHECK-NEXT: LV(REG): Found invariant usage: 2 item
2122
; CHECK-NEXT: LV(REG): RegisterClass: Generic::ScalarRC, 2 registers
2223
; CHECK-NEXT: LV(REG): RegisterClass: Generic::VectorRC, 8 registers

‎llvm/test/Transforms/LoopVectorize/LoongArch/reg-usage.ll

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -15,8 +15,9 @@ define void @bar(ptr %A, i32 signext %n) {
1515
; CHECK-SCALAR-NEXT: LV(REG): RegisterClass: LoongArch::GPRRC, 1 registers
1616
; CHECK-SCALAR-NEXT: LV: The target has 30 registers of LoongArch::GPRRC register class
1717
; CHECK-SCALAR-NEXT: LV: The target has 32 registers of LoongArch::FPRRC register class
18-
; CHECK-VECTOR: LV(REG): Found max usage: 1 item
18+
; CHECK-VECTOR: LV(REG): Found max usage: 2 item
1919
; CHECK-VECTOR-NEXT: LV(REG): RegisterClass: LoongArch::VRRC, 3 registers
20+
; CHECK-VECTOR-NEXT: LV(REG): RegisterClass: LoongArch::GPRRC, 1 registers
2021
; CHECK-VECTOR-NEXT: LV(REG): Found invariant usage: 1 item
2122
; CHECK-VECTOR-NEXT: LV(REG): RegisterClass: LoongArch::GPRRC, 1 registers
2223
; CHECK-VECTOR-NEXT: LV: The target has 32 registers of LoongArch::VRRC register class

‎llvm/test/Transforms/LoopVectorize/PowerPC/reg-usage.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -179,7 +179,7 @@ define void @double_(ptr nocapture %A, i32 %n) nounwind uwtable ssp {
179179

180180
;CHECK-PWR9: LV(REG): VF = 1
181181
;CHECK-PWR9: LV(REG): Found max usage: 2 item
182-
;CHECK-PWR9-NEXT: LV(REG): RegisterClass: PPC::GPRRC, 2 registers
182+
;CHECK-PWR9-NEXT: LV(REG): RegisterClass: PPC::GPRRC, 3 registers
183183
;CHECK-PWR9-NEXT: LV(REG): RegisterClass: PPC::VSXRC, 5 registers
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;CHECK-PWR9: LV(REG): Found invariant usage: 1 item
185185
;CHECK-PWR9-NEXT: LV(REG): RegisterClass: PPC::GPRRC, 1 registers
@@ -248,7 +248,7 @@ define void @fp16_(ptr nocapture readonly %pIn, ptr nocapture %pOut, i32 %numRow
248248
;CHECK-LABEL: fp16_
249249
;CHECK: LV(REG): VF = 1
250250
;CHECK: LV(REG): Found max usage: 2 item
251-
;CHECK: LV(REG): RegisterClass: PPC::GPRRC, 4 registers
251+
;CHECK: LV(REG): RegisterClass: PPC::GPRRC, 5 registers
252252
;CHECK: LV(REG): RegisterClass: PPC::VSXRC, 2 registers
253253
entry:
254254
%tmp.0.extract.trunc = trunc i32 %scale.coerce to i16

‎llvm/test/Transforms/LoopVectorize/RISCV/riscv-vector-reverse.ll

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -128,8 +128,9 @@ define void @vector_reverse_i64(ptr nocapture noundef writeonly %A, ptr nocaptur
128128
; CHECK-NEXT: LV(REG): At #5 Interval # 3
129129
; CHECK-NEXT: LV(REG): At #6 Interval # 3
130130
; CHECK-NEXT: LV(REG): At #7 Interval # 3
131-
; CHECK-NEXT: LV(REG): At #9 Interval # 1
132-
; CHECK-NEXT: LV(REG): At #10 Interval # 2
131+
; CHECK-NEXT: LV(REG): At #8 Interval # 3
132+
; CHECK-NEXT: LV(REG): At #9 Interval # 2
133+
; CHECK-NEXT: LV(REG): At #10 Interval # 3
133134
; CHECK-NEXT: LV(REG): VF = vscale x 4
134135
; CHECK-NEXT: LV(REG): Found max usage: 2 item
135136
; CHECK-NEXT: LV(REG): RegisterClass: RISCV::GPRRC, 3 registers
@@ -377,8 +378,9 @@ define void @vector_reverse_f32(ptr nocapture noundef writeonly %A, ptr nocaptur
377378
; CHECK-NEXT: LV(REG): At #5 Interval # 3
378379
; CHECK-NEXT: LV(REG): At #6 Interval # 3
379380
; CHECK-NEXT: LV(REG): At #7 Interval # 3
380-
; CHECK-NEXT: LV(REG): At #9 Interval # 1
381-
; CHECK-NEXT: LV(REG): At #10 Interval # 2
381+
; CHECK-NEXT: LV(REG): At #8 Interval # 3
382+
; CHECK-NEXT: LV(REG): At #9 Interval # 2
383+
; CHECK-NEXT: LV(REG): At #10 Interval # 3
382384
; CHECK-NEXT: LV(REG): VF = vscale x 4
383385
; CHECK-NEXT: LV(REG): Found max usage: 2 item
384386
; CHECK-NEXT: LV(REG): RegisterClass: RISCV::GPRRC, 3 registers

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