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[LLVM][CodeGen][SVE] Increase vector.insert test coverage.
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‎llvm/test/CodeGen/AArch64/sve-insert-scalable-vector.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s | FileCheck %s
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target triple = "aarch64-unknown-linux-gnu"
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; half vectors
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define <vscale x 4 x half> @insert_into_poison_nxv4f16_nxv2f16_0(<vscale x 2 x half> %a) #0 {
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; CHECK-LABEL: insert_into_poison_nxv4f16_nxv2f16_0:
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; CHECK: // %bb.0:
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; CHECK-NEXT: uunpkhi z1.d, z0.s
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; CHECK-NEXT: uzp1 z0.s, z0.s, z1.s
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; CHECK-NEXT: ret
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%res = call <vscale x 4 x half> @llvm.vector.insert.nxv4f16.nxv2f16(<vscale x 4 x half> poison, <vscale x 2 x half> %a, i64 0)
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ret <vscale x 4 x half> %res
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}
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define <vscale x 4 x half> @insert_into_poison_nxv4f16_nxv2f16_2(<vscale x 2 x half> %a) #0 {
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; CHECK-LABEL: insert_into_poison_nxv4f16_nxv2f16_2:
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; CHECK: // %bb.0:
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; CHECK-NEXT: uunpklo z1.d, z0.s
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; CHECK-NEXT: uzp1 z0.s, z1.s, z0.s
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; CHECK-NEXT: ret
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%res = call <vscale x 4 x half> @llvm.vector.insert.nxv4f16.nxv2f16(<vscale x 4 x half> poison, <vscale x 2 x half> %a, i64 2)
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ret <vscale x 4 x half> %res
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}
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define <vscale x 8 x half> @insert_into_poison_nxv8f16_nxv2f16_0(<vscale x 2 x half> %a) #0 {
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; CHECK-LABEL: insert_into_poison_nxv8f16_nxv2f16_0:
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; CHECK: // %bb.0:
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; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
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; CHECK-NEXT: addvl sp, sp, #-1
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; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 8 * VG
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; CHECK-NEXT: .cfi_offset w29, -16
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: ptrue p1.h
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; CHECK-NEXT: st1h { z0.d }, p0, [sp]
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; CHECK-NEXT: ld1h { z0.h }, p1/z, [sp]
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; CHECK-NEXT: addvl sp, sp, #1
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; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
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; CHECK-NEXT: ret
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%res = call <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv2f16(<vscale x 8 x half> poison, <vscale x 2 x half> %a, i64 0)
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ret <vscale x 8 x half> %res
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}
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define <vscale x 8 x half> @insert_into_poison_nxv8f16_nxv2f16_2(<vscale x 2 x half> %a) #0 {
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; CHECK-LABEL: insert_into_poison_nxv8f16_nxv2f16_2:
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; CHECK: // %bb.0:
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; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
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; CHECK-NEXT: addvl sp, sp, #-1
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; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 8 * VG
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; CHECK-NEXT: .cfi_offset w29, -16
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: ptrue p1.h
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; CHECK-NEXT: st1h { z0.d }, p0, [sp, #1, mul vl]
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; CHECK-NEXT: ld1h { z0.h }, p1/z, [sp]
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; CHECK-NEXT: addvl sp, sp, #1
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; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
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; CHECK-NEXT: ret
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%res = call <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv2f16(<vscale x 8 x half> poison, <vscale x 2 x half> %a, i64 2)
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ret <vscale x 8 x half> %res
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}
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define <vscale x 8 x half> @insert_into_poison_nxv8f16_nxv2f16_4(<vscale x 2 x half> %a) #0 {
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; CHECK-LABEL: insert_into_poison_nxv8f16_nxv2f16_4:
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; CHECK: // %bb.0:
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; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
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; CHECK-NEXT: addvl sp, sp, #-1
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; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 8 * VG
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; CHECK-NEXT: .cfi_offset w29, -16
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: ptrue p1.h
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; CHECK-NEXT: st1h { z0.d }, p0, [sp, #2, mul vl]
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; CHECK-NEXT: ld1h { z0.h }, p1/z, [sp]
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; CHECK-NEXT: addvl sp, sp, #1
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; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
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; CHECK-NEXT: ret
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%res = call <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv2f16(<vscale x 8 x half> poison, <vscale x 2 x half> %a, i64 4)
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ret <vscale x 8 x half> %res
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}
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define <vscale x 8 x half> @insert_into_poison_nxv8f16_nxv2f16_6(<vscale x 2 x half> %a) #0 {
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; CHECK-LABEL: insert_into_poison_nxv8f16_nxv2f16_6:
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; CHECK: // %bb.0:
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; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
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; CHECK-NEXT: addvl sp, sp, #-1
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; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 8 * VG
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; CHECK-NEXT: .cfi_offset w29, -16
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: ptrue p1.h
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; CHECK-NEXT: st1h { z0.d }, p0, [sp, #3, mul vl]
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; CHECK-NEXT: ld1h { z0.h }, p1/z, [sp]
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; CHECK-NEXT: addvl sp, sp, #1
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; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
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; CHECK-NEXT: ret
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%res = call <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv2f16(<vscale x 8 x half> poison, <vscale x 2 x half> %a, i64 6)
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ret <vscale x 8 x half> %res
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}
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define <vscale x 8 x half> @insert_into_poison_nxv8f16_nxv4f16_0(<vscale x 4 x half> %a) #0 {
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; CHECK-LABEL: insert_into_poison_nxv8f16_nxv4f16_0:
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; CHECK: // %bb.0:
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; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h
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; CHECK-NEXT: ret
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%res = call <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv4f16(<vscale x 8 x half> poison, <vscale x 4 x half> %a, i64 0)
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ret <vscale x 8 x half> %res
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}
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define <vscale x 8 x half> @insert_into_poison_nxv8f16_nxv4f16_4(<vscale x 4 x half> %a) #0 {
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; CHECK-LABEL: insert_into_poison_nxv8f16_nxv4f16_4:
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; CHECK: // %bb.0:
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; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h
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; CHECK-NEXT: ret
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%res = call <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv4f16(<vscale x 8 x half> poison, <vscale x 4 x half> %a, i64 4)
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ret <vscale x 8 x half> %res
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}
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; float vectors
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define <vscale x 4 x float> @insert_into_poison_nxv4f32_nxv2f32_0(<vscale x 2 x float> %a) #0 {
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; CHECK-LABEL: insert_into_poison_nxv4f32_nxv2f32_0:
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; CHECK: // %bb.0:
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; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s
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; CHECK-NEXT: ret
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%res = call <vscale x 4 x float> @llvm.vector.insert.nxv4f32.nxv2f32(<vscale x 4 x float> poison, <vscale x 2 x float> %a, i64 0)
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ret <vscale x 4 x float> %res
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}
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define <vscale x 4 x float> @insert_into_poison_nxv4f32_nxv2f32_2(<vscale x 2 x float> %a) #0 {
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; CHECK-LABEL: insert_into_poison_nxv4f32_nxv2f32_2:
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; CHECK: // %bb.0:
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; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s
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; CHECK-NEXT: ret
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%res = call <vscale x 4 x float> @llvm.vector.insert.nxv4f32.nxv2f32(<vscale x 4 x float> poison, <vscale x 2 x float> %a, i64 2)
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ret <vscale x 4 x float> %res
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}
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; bfloat vectors
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define <vscale x 4 x bfloat> @insert_into_poison_nxv4bf16_nxv2bf16_0(<vscale x 2 x bfloat> %a) #0 {
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; CHECK-LABEL: insert_into_poison_nxv4bf16_nxv2bf16_0:
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; CHECK: // %bb.0:
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; CHECK-NEXT: uunpkhi z1.d, z0.s
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; CHECK-NEXT: uzp1 z0.s, z0.s, z1.s
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; CHECK-NEXT: ret
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%res = call <vscale x 4 x bfloat> @llvm.vector.insert.nxv4bf16.nxv2bf16(<vscale x 4 x bfloat> poison, <vscale x 2 x bfloat> %a, i64 0)
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ret <vscale x 4 x bfloat> %res
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}
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define <vscale x 4 x bfloat> @insert_into_poison_nxv4bf16_nxv2bf16_2(<vscale x 2 x bfloat> %a) #0 {
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; CHECK-LABEL: insert_into_poison_nxv4bf16_nxv2bf16_2:
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; CHECK: // %bb.0:
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; CHECK-NEXT: uunpklo z1.d, z0.s
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; CHECK-NEXT: uzp1 z0.s, z1.s, z0.s
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; CHECK-NEXT: ret
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%res = call <vscale x 4 x bfloat> @llvm.vector.insert.nxv4bf16.nxv2bf16(<vscale x 4 x bfloat> poison, <vscale x 2 x bfloat> %a, i64 2)
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ret <vscale x 4 x bfloat> %res
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}
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define <vscale x 8 x bfloat> @insert_into_poison_nxv8bf16_nxv2bf16_0(<vscale x 2 x bfloat> %a) #0 {
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; CHECK-LABEL: insert_into_poison_nxv8bf16_nxv2bf16_0:
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; CHECK: // %bb.0:
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; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
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; CHECK-NEXT: addvl sp, sp, #-1
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; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 8 * VG
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; CHECK-NEXT: .cfi_offset w29, -16
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: ptrue p1.h
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; CHECK-NEXT: st1h { z0.d }, p0, [sp]
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; CHECK-NEXT: ld1h { z0.h }, p1/z, [sp]
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; CHECK-NEXT: addvl sp, sp, #1
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; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
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; CHECK-NEXT: ret
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%res = call <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv2bf16(<vscale x 8 x bfloat> poison, <vscale x 2 x bfloat> %a, i64 0)
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ret <vscale x 8 x bfloat> %res
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}
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define <vscale x 8 x bfloat> @insert_into_poison_nxv8bf16_nxv2bf16_2(<vscale x 2 x bfloat> %a) #0 {
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; CHECK-LABEL: insert_into_poison_nxv8bf16_nxv2bf16_2:
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; CHECK: // %bb.0:
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; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
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; CHECK-NEXT: addvl sp, sp, #-1
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; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 8 * VG
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; CHECK-NEXT: .cfi_offset w29, -16
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: ptrue p1.h
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; CHECK-NEXT: st1h { z0.d }, p0, [sp, #1, mul vl]
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; CHECK-NEXT: ld1h { z0.h }, p1/z, [sp]
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; CHECK-NEXT: addvl sp, sp, #1
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; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
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; CHECK-NEXT: ret
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%res = call <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv2bf16(<vscale x 8 x bfloat> poison, <vscale x 2 x bfloat> %a, i64 2)
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ret <vscale x 8 x bfloat> %res
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}
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define <vscale x 8 x bfloat> @insert_into_poison_nxv8bf16_nxv2bf16_4(<vscale x 2 x bfloat> %a) #0 {
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; CHECK-LABEL: insert_into_poison_nxv8bf16_nxv2bf16_4:
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; CHECK: // %bb.0:
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; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
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; CHECK-NEXT: addvl sp, sp, #-1
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; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 8 * VG
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; CHECK-NEXT: .cfi_offset w29, -16
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: ptrue p1.h
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; CHECK-NEXT: st1h { z0.d }, p0, [sp, #2, mul vl]
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; CHECK-NEXT: ld1h { z0.h }, p1/z, [sp]
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; CHECK-NEXT: addvl sp, sp, #1
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; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
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; CHECK-NEXT: ret
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%res = call <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv2bf16(<vscale x 8 x bfloat> poison, <vscale x 2 x bfloat> %a, i64 4)
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ret <vscale x 8 x bfloat> %res
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}
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define <vscale x 8 x bfloat> @insert_into_poison_nxv8bf16_nxv2bf16_6(<vscale x 2 x bfloat> %a) #0 {
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; CHECK-LABEL: insert_into_poison_nxv8bf16_nxv2bf16_6:
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; CHECK: // %bb.0:
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; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
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; CHECK-NEXT: addvl sp, sp, #-1
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; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 8 * VG
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; CHECK-NEXT: .cfi_offset w29, -16
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: ptrue p1.h
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; CHECK-NEXT: st1h { z0.d }, p0, [sp, #3, mul vl]
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; CHECK-NEXT: ld1h { z0.h }, p1/z, [sp]
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; CHECK-NEXT: addvl sp, sp, #1
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; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
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; CHECK-NEXT: ret
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%res = call <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv2bf16(<vscale x 8 x bfloat> poison, <vscale x 2 x bfloat> %a, i64 6)
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ret <vscale x 8 x bfloat> %res
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}
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define <vscale x 8 x bfloat> @insert_into_poison_nxv8bf16_nxv4bf16_0(<vscale x 4 x bfloat> %a) #0 {
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; CHECK-LABEL: insert_into_poison_nxv8bf16_nxv4bf16_0:
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; CHECK: // %bb.0:
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; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h
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; CHECK-NEXT: ret
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%res = call <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv4bf16(<vscale x 8 x bfloat> poison, <vscale x 4 x bfloat> %a, i64 0)
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ret <vscale x 8 x bfloat> %res
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}
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define <vscale x 8 x bfloat> @insert_into_poison_nxv8bf16_nxv4bf16_4(<vscale x 4 x bfloat> %a) #0 {
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; CHECK-LABEL: insert_into_poison_nxv8bf16_nxv4bf16_4:
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; CHECK: // %bb.0:
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; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h
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; CHECK-NEXT: ret
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%res = call <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv4bf16(<vscale x 8 x bfloat> poison, <vscale x 4 x bfloat> %a, i64 4)
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ret <vscale x 8 x bfloat> %res
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}
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attributes #0 = { "target-features"="+sve,+bf16" }
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declare <vscale x 4 x half> @llvm.vector.insert.nxv4f16.nxv2f16(<vscale x 4 x half>, <vscale x 2 x half>, i64)
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declare <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv2f16(<vscale x 8 x half>, <vscale x 2 x half>, i64)
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declare <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv4f16(<vscale x 8 x half>, <vscale x 4 x half>, i64)
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declare <vscale x 4 x float> @llvm.vector.insert.nxv4f32.nxv2f32(<vscale x 4 x float>, <vscale x 2 x float>, i64)
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declare <vscale x 4 x bfloat> @llvm.vector.insert.nxv4bf16.nxv2bf16(<vscale x 4 x bfloat>, <vscale x 2 x bfloat>, i64)
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declare <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv2bf16(<vscale x 8 x bfloat>, <vscale x 2 x bfloat>, i64)
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declare <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv4bf16(<vscale x 8 x bfloat>, <vscale x 4 x bfloat>, i64)
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