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[AArch64] Add assembly/disassembly for FMOP4A (widening, 2-way, FP8 to FP16) instructions
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‎llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td

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@@ -1016,6 +1016,7 @@ let Predicates = [HasSME2p2, HasSMEF8F32], Uses = [FPMR, FPCR] in {
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let Predicates = [HasSME2p2, HasSMEF8F16], Uses = [FPMR, FPCR] in {
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def FTMOPA_M2ZZZI_BtoH : sme_tmopa_16b<0b01001, ZZ_b_mul_r, ZPR8, "ftmopa">;
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defm FMOP4A : sme2_fmop4a_fp8_fp16_2way<"fmop4a">;
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} // [HasSME2p2, HasSMEF8F16], Uses = [FPMR, FPCR]
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let Predicates = [HasSME2p2, HasSMEF16F16] in {

‎llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

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@@ -6261,6 +6261,8 @@ bool AArch64AsmParser::showMatchError(SMLoc Loc, unsigned ErrCode,
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case Match_InvalidMatrixTileVectorV128:
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return Error(Loc,
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"invalid matrix operand, expected za[0-15]h.q or za[0-15]v.q");
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case Match_InvalidMatrixTile16:
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return Error(Loc, "invalid matrix operand, expected za[0-1].h");
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case Match_InvalidMatrixTile32:
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return Error(Loc, "invalid matrix operand, expected za[0-3].s");
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case Match_InvalidMatrixTile64:
@@ -6881,6 +6883,7 @@ bool AArch64AsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
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case Match_InvalidSVEExactFPImmOperandHalfOne:
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case Match_InvalidSVEExactFPImmOperandHalfTwo:
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case Match_InvalidSVEExactFPImmOperandZeroOne:
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case Match_InvalidMatrixTile16:
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case Match_InvalidMatrixTile32:
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case Match_InvalidMatrixTile64:
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case Match_InvalidMatrix:

‎llvm/lib/Target/AArch64/SMEInstrFormats.td

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@@ -5188,3 +5188,38 @@ class sme2_luti4_vector_vg4_strided<bits<2> sz, bits<2> op, string mnemonic>
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let Inst{3-2} = 0b00;
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let Inst{1-0} = Zd{1-0};
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}
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class sme2_fp8_fp16_quarter_tile_outer_product<bit M, bit N, string mnemonic, RegisterOperand zn_ty, RegisterOperand zm_ty>
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: I<(outs TileOp16:$ZAda),
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(ins TileOp16:$_ZAda, zn_ty:$Zn, zm_ty:$Zm),
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mnemonic, "\t$ZAda, $Zn, $Zm",
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"", []>, Sched<[]> {
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bit ZAda;
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bits<3> Zn;
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bits<3> Zm;
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let Inst{31-21} = 0b10000000001;
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let Inst{20} = M;
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let Inst{19-17} = Zm;
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let Inst{16-10} = 0b0000000;
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let Inst{9} = N;
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let Inst{8-6} = Zn;
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let Inst{5-1} = 0b00100;
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let Inst{0} = ZAda;
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let Constraints = "$ZAda = $_ZAda";
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}
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multiclass sme2_fmop4a_fp8_fp16_2way<string mnemonic> {
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// Single vectors
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def _MZZ_BtoH : sme2_fp8_fp16_quarter_tile_outer_product<0, 0, mnemonic, ZPR8Mul2_Lo, ZPR8Mul2_Hi>;
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// Multiple and single vectors
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def _M2ZZ_BtoH : sme2_fp8_fp16_quarter_tile_outer_product<0, 1, mnemonic, ZZ_b_mul_r_Lo, ZPR8Mul2_Hi>;
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// Single and multiple vectors
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def _MZ2Z_BtoH : sme2_fp8_fp16_quarter_tile_outer_product<1, 0, mnemonic, ZPR8Mul2_Lo, ZZ_b_mul_r_Hi>;
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// Multiple vectors
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def _M2Z2Z_BtoH : sme2_fp8_fp16_quarter_tile_outer_product<1, 1, mnemonic, ZZ_b_mul_r_Lo, ZZ_b_mul_r_Hi>;
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}

‎llvm/test/MC/AArch64/SME2p2/fmop4a-fp8-fp16-widening-diagnostics.s

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// RUN: not llvm-mc -triple=aarch64 -mattr=+sme2p2,+sme-f8f16 < %s 2>&1 | FileCheck %s
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// Single vectors
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fmop4a za0.d, z0.b, z16.b
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand
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fmop4a za2.h, z0.b, z16.b
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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fmop4a za0.h, z0.s, z16.b
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.b..z14.b
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fmop4a za0.h, z15.b, z16.b
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.b..z14.b
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fmop4a za0.h, z16.b, z16.b
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.b..z14.b
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fmop4a za0.h, z0.b, z16.s
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.b..z30.b
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fmop4a za0.h, z12.b, z17.b
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.b..z30.b
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fmop4a za0.h, z12.b, z14.b
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.b..z30.b
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fmop4a za0.h, z12.b, z31.b
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.b..z30.b
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// Single and multiple vectors
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fmop4a za0.d, z0.b, {z16.b-z17.b}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand
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fmop4a za2.h, z0.b, {z16.b-z17.b}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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fmop4a za0.h, z0.s, {z16.b-z17.b}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.b..z14.b
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fmop4a za0.h, z1.b, {z16.b-z17.b}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.b..z14.b
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fmop4a za0.h, z16.b, {z16.b-z17.b}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.b..z14.b
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fmop4a za0.h, z0.b, {z16.s-z17.s}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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fmop4a za0.h, z0.b, {z17.b-z18.b}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z16-z30, where the first vector is a multiple of 2 and with matching element types
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fmop4a za0.h, z0.b, {z16.b-z18.b}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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fmop4a za0.h, z0.b, {z12.b-z13.b}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z16-z30, where the first vector is a multiple of 2 and with matching element types
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// Multiple and single vectors
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fmop4a za0.d, {z0.b-z1.b}, z16.b
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand
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fmop4a za2.h, {z0.b-z1.b}, z16.b
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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fmop4a za0.h, {z0.s-z1.b}, z16.b
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix
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fmop4a za0.h, {z1.b-z2.b}, z16.b
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z0-z14, where the first vector is a multiple of 2 and with matching element types
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fmop4a za2.h, {z0.b-z2.b}, z16.b
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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fmop4a za0.h, {z16.b-z17.b}, z16.b
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z0-z14, where the first vector is a multiple of 2 and with matching element types
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fmop4a za0.h, {z0.b-z1.b}, z16.d
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.b..z30.b
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fmop4a za0.h, {z0.b-z1.b}, z17.b
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.b..z30.b
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fmop4a za0.h, {z0.b-z1.b}, z12.b
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.b..z30.b
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// Multiple vectors
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fmop4a za0.d, {z0.b-z1.b}, {z16.b-z17.b}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand
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fmop4a za2.h, {z0.b-z1.b}, {z16.b-z17.b}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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fmop4a za0.h, {z0.s-z1.s}, {z16.b-z17.b}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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fmop4a za0.h, {z1.b-z2.b}, {z16.b-z17.b}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z0-z14, where the first vector is a multiple of 2 and with matching element types
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fmop4a za0.h, {z0.b-z2.b}, {z16.b-z17.b}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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fmop4a za0.h, {z18.b-z19.b}, {z16.b-z17.b}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z0-z14, where the first vector is a multiple of 2 and with matching element types
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fmop4a za0.h, {z0.b-z1.b}, {z16.s-z17.s}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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fmop4a za0.h, {z0.b-z1.b}, {z19.b-z20.b}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z16-z30, where the first vector is a multiple of 2 and with matching element types
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fmop4a za0.h, {z0.b-z1.b}, {z18.b-z20.b}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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fmop4a za0.h, {z0.b-z1.b}, {z10.b-z11.b}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z16-z30, where the first vector is a multiple of 2 and with matching element types

‎llvm/test/MC/AArch64/SME2p2/fmop4a-fp8-fp16-widening.s

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// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2,+sme-f8f16 < %s \
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// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
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// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
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// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
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// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p2,+sme-f8f16 < %s \
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// RUN: | llvm-objdump -d --mattr=+sme2p2,+sme-f8f16 - | FileCheck %s --check-prefix=CHECK-INST
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// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p2,+sme-f8f16 < %s \
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// RUN: | llvm-objdump -d --mattr=-sme2p2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
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// Disassemble encoding and check the re-encoding (-show-encoding) matches.
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// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2,+sme-f8f16 < %s \
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// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
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// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p2,+sme-f8f16 -disassemble -show-encoding \
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// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
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// Single vectors
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fmop4a za0.h, z0.b, z16.b // 10000000-00100000-00000000-00001000
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// CHECK-INST: fmop4a za0.h, z0.b, z16.b
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// CHECK-ENCODING: [0x08,0x00,0x20,0x80]
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// CHECK-ERROR: instruction requires: sme2p2 sme-f8f16
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// CHECK-UNKNOWN: 80200008 <unknown>
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fmop4a za1.h, z12.b, z24.b // 10000000-00101000-00000001-10001001
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// CHECK-INST: fmop4a za1.h, z12.b, z24.b
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// CHECK-ENCODING: [0x89,0x01,0x28,0x80]
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// CHECK-ERROR: instruction requires: sme2p2 sme-f8f16
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// CHECK-UNKNOWN: 80280189 <unknown>
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fmop4a za1.h, z14.b, z30.b // 10000000-00101110-00000001-11001001
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// CHECK-INST: fmop4a za1.h, z14.b, z30.b
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// CHECK-ENCODING: [0xc9,0x01,0x2e,0x80]
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// CHECK-ERROR: instruction requires: sme2p2 sme-f8f16
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// CHECK-UNKNOWN: 802e01c9 <unknown>
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// Single and multiple vectors
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fmop4a za0.h, z0.b, {z16.b-z17.b} // 10000000-00110000-00000000-00001000
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// CHECK-INST: fmop4a za0.h, z0.b, { z16.b, z17.b }
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// CHECK-ENCODING: [0x08,0x00,0x30,0x80]
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// CHECK-ERROR: instruction requires: sme2p2 sme-f8f16
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// CHECK-UNKNOWN: 80300008 <unknown>
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fmop4a za1.h, z10.b, {z20.b-z21.b} // 10000000-00110100-00000001-01001001
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// CHECK-INST: fmop4a za1.h, z10.b, { z20.b, z21.b }
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// CHECK-ENCODING: [0x49,0x01,0x34,0x80]
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// CHECK-ERROR: instruction requires: sme2p2 sme-f8f16
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// CHECK-UNKNOWN: 80340149 <unknown>
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fmop4a za1.h, z14.b, {z30.b-z31.b} // 10000000-00111110-00000001-11001001
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// CHECK-INST: fmop4a za1.h, z14.b, { z30.b, z31.b }
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// CHECK-ENCODING: [0xc9,0x01,0x3e,0x80]
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// CHECK-ERROR: instruction requires: sme2p2 sme-f8f16
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// CHECK-UNKNOWN: 803e01c9 <unknown>
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// Multiple and single vectors
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fmop4a za0.h, {z0.b-z1.b}, z16.b // 10000000-00100000-00000010-00001000
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// CHECK-INST: fmop4a za0.h, { z0.b, z1.b }, z16.b
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// CHECK-ENCODING: [0x08,0x02,0x20,0x80]
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// CHECK-ERROR: instruction requires: sme2p2 sme-f8f16
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// CHECK-UNKNOWN: 80200208 <unknown>
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fmop4a za1.h, {z10.b-z11.b}, z20.b // 10000000-00100100-00000011-01001001
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// CHECK-INST: fmop4a za1.h, { z10.b, z11.b }, z20.b
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// CHECK-ENCODING: [0x49,0x03,0x24,0x80]
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// CHECK-ERROR: instruction requires: sme2p2 sme-f8f16
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// CHECK-UNKNOWN: 80240349 <unknown>
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fmop4a za1.h, {z14.b-z15.b}, z30.b // 10000000-00101110-00000011-11001001
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// CHECK-INST: fmop4a za1.h, { z14.b, z15.b }, z30.b
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// CHECK-ENCODING: [0xc9,0x03,0x2e,0x80]
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// CHECK-ERROR: instruction requires: sme2p2 sme-f8f16
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// CHECK-UNKNOWN: 802e03c9 <unknown>
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// Multiple vectors
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fmop4a za0.h, {z0.b-z1.b}, {z16.b-z17.b} // 10000000-00110000-00000010-00001000
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// CHECK-INST: fmop4a za0.h, { z0.b, z1.b }, { z16.b, z17.b }
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// CHECK-ENCODING: [0x08,0x02,0x30,0x80]
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// CHECK-ERROR: instruction requires: sme2p2 sme-f8f16
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// CHECK-UNKNOWN: 80300208 <unknown>
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fmop4a za1.h, {z10.b-z11.b}, {z20.b-z21.b} // 10000000-00110100-00000011-01001001
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// CHECK-INST: fmop4a za1.h, { z10.b, z11.b }, { z20.b, z21.b }
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// CHECK-ENCODING: [0x49,0x03,0x34,0x80]
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// CHECK-ERROR: instruction requires: sme2p2 sme-f8f16
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// CHECK-UNKNOWN: 80340349 <unknown>
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fmop4a za1.h, {z14.b-z15.b}, {z30.b-z31.b} // 10000000-00111110-00000011-11001001
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// CHECK-INST: fmop4a za1.h, { z14.b, z15.b }, { z30.b, z31.b }
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// CHECK-ENCODING: [0xc9,0x03,0x3e,0x80]
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// CHECK-ERROR: instruction requires: sme2p2 sme-f8f16
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// CHECK-UNKNOWN: 803e03c9 <unknown>
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