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[test] Remove redundant -march= when target triple is specified in IR
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-42
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‎llvm/test/CodeGen/AArch64/stack-tagging-ex-2.ll

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; clang -target aarch64-eabi -O2 -march=armv8.5-a+memtag -fsanitize=memtag -S -emit-llvm test.cc
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; clang -target aarch64-eabi -O2 -fsanitize=memtag -S -emit-llvm test.cc
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; void bar() {
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; throw 42;
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; }

‎llvm/test/CodeGen/Hexagon/autohvx/float-cost.ll

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; RUN: opt -march=hexagon -passes=loop-vectorize -hexagon-autohvx -debug-only=loop-vectorize -S < %s 2>&1 | FileCheck %s
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; RUN: opt -passes=loop-vectorize -hexagon-autohvx -debug-only=loop-vectorize -S < %s 2>&1 | FileCheck %s
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; REQUIRES: asserts
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; Check that the cost model makes vectorization non-profitable.

‎llvm/test/CodeGen/Hexagon/autohvx/interleave.ll

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; RUN: opt -march=hexagon -hexagon-autohvx -passes=loop-vectorize -S < %s | FileCheck %s
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; RUN: opt -hexagon-autohvx -passes=loop-vectorize -S < %s | FileCheck %s
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; Check that the loop has been interleaved.
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; CHECK: store <64 x i32> %interleaved.vec
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‎llvm/test/CodeGen/Hexagon/autohvx/maximize-bandwidth.ll

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; RUN: opt -march=hexagon -hexagon-autohvx -passes=loop-vectorize -S < %s | FileCheck %s
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; RUN: opt -hexagon-autohvx -passes=loop-vectorize -S < %s | FileCheck %s
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; Check that the loop is vectorized with VF=32.
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; CHECK: wide.load{{.*}} = load <32 x i32>
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; CHECK: wide.load{{.*}} = load <32 x i16>

‎llvm/test/CodeGen/Hexagon/bug15515-shuffle.ll

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; RUN: opt -march=hexagon -O2 -S < %s
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; RUN: opt -O2 -S < %s
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; REQUIRES: asserts
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;
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; -fvectorize-loops infinite compile/memory

‎llvm/test/CodeGen/Hexagon/const-pool-tf.ll

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; RUN: opt -relocation-model pic -mtriple=hexagon -mcpu=hexagonv60 -O2 -S < %s | llc -march=hexagon -mcpu=hexagonv60 -relocation-model pic
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; RUN: opt -relocation-model pic -mtriple=hexagon -mcpu=hexagonv60 -O2 -S < %s | llc -mcpu=hexagonv60 -relocation-model pic
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; CHECK: jumpr
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‎llvm/test/CodeGen/Hexagon/glob-align-volatile.ll

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; RUN: opt -Os -march=hexagon -S < %s | FileCheck %s
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; RUN: opt -Os -S < %s | FileCheck %s
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; Don't reset the alignment on the struct to 1.
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; CHECK: align 4
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‎llvm/test/CodeGen/Hexagon/loop-idiom/pmpy-infinite-loop.ll

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; RUN: opt -march=hexagon -hexagon-loop-idiom -S < %s | FileCheck %s
2-
; RUN: opt -march=hexagon -p hexagon-loop-idiom -S < %s | FileCheck %s
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; RUN: opt -hexagon-loop-idiom -S < %s | FileCheck %s
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; RUN: opt -p hexagon-loop-idiom -S < %s | FileCheck %s
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; CHECK-LABEL: define void @fred
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55
; Check that this test does not crash.

‎llvm/test/CodeGen/Hexagon/loop-idiom/pmpy-long-loop.ll

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; RUN: opt -march=hexagon -hexagon-loop-idiom -S < %s | FileCheck %s
2-
; RUN: opt -march=hexagon -p hexagon-loop-idiom -S < %s | FileCheck %s
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; RUN: opt -hexagon-loop-idiom -S < %s | FileCheck %s
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; RUN: opt -p hexagon-loop-idiom -S < %s | FileCheck %s
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;
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; The number of nested selects caused the simplification loop to take
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; more than the maximum number of iterations. This caused the compiler

‎llvm/test/CodeGen/Hexagon/loop-idiom/pmpy-mod.ll

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; the Hexagon loop idiom recognition runs. This is to check that we still
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; get this opportunity regardless of what happens before.
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5-
; RUN: opt -O2 -march=hexagon -S < %s | FileCheck %s
6-
; RUN: opt -passes='default<O2>' -march=hexagon -S < %s | FileCheck %s
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; RUN: opt -O2 -S < %s | FileCheck %s
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; RUN: opt -passes='default<O2>' -S < %s | FileCheck %s
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target triple = "hexagon"
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target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"

‎llvm/test/CodeGen/Hexagon/loop-idiom/pmpy-shiftconv-fail.ll

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; RUN: opt -march=hexagon -hexagon-loop-idiom -S < %s | FileCheck %s
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; RUN: opt -march=hexagon -p hexagon-loop-idiom -S < %s | FileCheck %s
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; RUN: opt -hexagon-loop-idiom -S < %s | FileCheck %s
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; RUN: opt -p hexagon-loop-idiom -S < %s | FileCheck %s
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; REQUIRES: asserts
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;
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; Check for sane output, this used to crash.

‎llvm/test/CodeGen/Hexagon/vcombine_zero_diff_ptrs.ll

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; RUN: opt -march=hexagon -hexagon-vc -S < %s | FileCheck %s
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; RUN: opt -hexagon-vc -S < %s | FileCheck %s
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; Test that the HexagonVectorCombine pass identifies instruction
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; pairs whose difference in pointers is zero. This creates a vector

‎llvm/test/CodeGen/Lanai/delay_filler.ll

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; RUN: llc -march=lanai < %s | FileCheck %s
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; RUN: llc -march=lanai --lanai-nop-delay-filler < %s | \
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; RUN: llc < %s | FileCheck %s
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; RUN: llc --lanai-nop-delay-filler < %s | \
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; RUN: FileCheck %s --check-prefix=NOP
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; CHECK: bt f

‎llvm/test/CodeGen/Lanai/lowering-128.ll

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; RUN: llc -march=lanai < %s | FileCheck %s
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; RUN: llc < %s | FileCheck %s
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; Tests that lowering wide registers (128 bits or more) works on Lanai.
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; The emitted assembly is not checked, we just do a smoketest.

‎llvm/test/CodeGen/NVPTX/surf-read.ll

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; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 -verify-machineinstrs | FileCheck %s
2-
; RUN: %if ptxas %{ llc < %s -march=nvptx64 -mcpu=sm_20 -verify-machineinstrs | %ptxas-verify %}
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; RUN: llc < %s -mcpu=sm_20 -verify-machineinstrs | FileCheck %s
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; RUN: %if ptxas %{ llc < %s -mcpu=sm_20 -verify-machineinstrs | %ptxas-verify %}
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4-
target triple = "nvptx-unknown-nvcl"
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target triple = "nvptx64-unknown-nvcl"
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declare i32 @llvm.nvvm.suld.1d.i32.trap(i64, i32)
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‎llvm/test/CodeGen/NVPTX/surf-write.ll

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; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 -verify-machineinstrs | FileCheck %s
2-
; RUN: %if ptxas %{ llc < %s -march=nvptx64 -mcpu=sm_20 -verify-machineinstrs | %ptxas-verify %}
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; RUN: llc < %s -mcpu=sm_20 -verify-machineinstrs | FileCheck %s
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; RUN: %if ptxas %{ llc < %s -mcpu=sm_20 -verify-machineinstrs | %ptxas-verify %}
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target triple = "nvptx-unknown-nvcl"
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‎llvm/test/CodeGen/NVPTX/tex-read.ll

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; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 -verify-machineinstrs | FileCheck %s
2-
; RUN: %if ptxas %{ llc < %s -march=nvptx64 -mcpu=sm_20 -verify-machineinstrs | %ptxas-verify %}
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; RUN: llc < %s -mcpu=sm_20 -verify-machineinstrs | FileCheck %s
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; RUN: %if ptxas %{ llc < %s -mcpu=sm_20 -verify-machineinstrs | %ptxas-verify %}
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4-
target triple = "nvptx-unknown-nvcl"
4+
target triple = "nvptx64-unknown-nvcl"
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declare { float, float, float, float } @llvm.nvvm.tex.1d.v4f32.s32(i64, i64, i32)
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‎llvm/test/CodeGen/PowerPC/ppc64le-aggregates.ll

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; Currently VSX support is disabled for this test because we generate lxsdx
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; instead of lfd, and stxsdx instead of stfd. That is a poor choice when we
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; have reg+imm addressing, and is on the list of things to be fixed.
11-
; The second run step is to ensure that -march=ppc64le is adequate to select
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; The second run step is to ensure that is adequate to select
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; the same feature set as with -mcpu=pwr8 since that is the baseline for ppc64le.
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target datalayout = "e-m:e-i64:64-n32:64"

‎llvm/test/CodeGen/Thumb2/bug-subw.ll

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; pr23772 - [ARM] r226200 can emit illegal thumb2 instruction: "sub sp, r12, #80"
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; RUN: llc -march=thumb -mcpu=cortex-m3 -O3 -filetype=asm -o - %s | FileCheck %s
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; RUN: llc -mcpu=cortex-m3 -O3 -filetype=asm -o - %s | FileCheck %s
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; CHECK-NOT: sub{{.*}} sp, r{{.*}}, #
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; CHECK: .fnend
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; TODO: Missed optimization. The three instructions generated to subtract SP can be converged to a single one

‎llvm/test/DebugInfo/NVPTX/debug-ptx-symbols.ll

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; RUN: llc < %s -march=nvptx64 -mcpu=sm_60 | FileCheck %s
2-
; RUN: %if ptxas %{ llc < %s -march=nvptx64 -mcpu=sm_60 | %ptxas-verify %}
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; RUN: llc < %s -mcpu=sm_60 | FileCheck %s
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; RUN: %if ptxas %{ llc < %s -mcpu=sm_60 | %ptxas-verify %}
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target datalayout = "e-i64:64-i128:128-v16:16-v32:32-n16:32:64"
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target triple = "nvptx64-nvidia-cuda"
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‎llvm/test/DebugInfo/X86/instr-ref-flag.ll

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; RUN: llc %s -o - -stop-before=finalize-isel -march=x86-64 \
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; RUN: llc %s -o - -stop-before=finalize-isel \
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; RUN: | FileCheck %s --check-prefixes=INSTRREFON
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; RUN: llc %s -o - -stop-before=finalize-isel -march=x86-64 \
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; RUN: llc %s -o - -stop-before=finalize-isel \
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; RUN: -experimental-debug-variable-locations=true \
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; RUN: | FileCheck %s --check-prefixes=INSTRREFON
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7-
; RUN: llc %s -o - -stop-before=finalize-isel -march=x86-64 \
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; RUN: llc %s -o - -stop-before=finalize-isel \
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; RUN: -experimental-debug-variable-locations=false \
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; RUN: | FileCheck %s --check-prefixes=INSTRREFOFF \
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; RUN: --implicit-check-not=DBG_INSTR_REF

‎llvm/test/DebugInfo/X86/no-entry-values-with-O0.ll

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; RUN: llc -O0 -dwarf-version=5 -debugger-tune=lldb -march=x86-64 -filetype=obj < %s \
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; RUN: llc -O0 -dwarf-version=5 -debugger-tune=lldb -filetype=obj < %s \
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; RUN: | llvm-dwarfdump - | FileCheck --implicit-check-not=DW_OP_entry_value %s
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; RUN: llc -O0 -dwarf-version=5 -debugger-tune=gdb -march=x86-64 -filetype=obj < %s \
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; RUN: llc -O0 -dwarf-version=5 -debugger-tune=gdb -filetype=obj < %s \
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; RUN: | llvm-dwarfdump - | FileCheck --implicit-check-not=DW_OP_entry_value %s
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; RUN: llc -force-instr-ref-livedebugvalues=1 -O0 -dwarf-version=5 -debugger-tune=lldb -march=x86-64 -filetype=obj < %s \
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; RUN: llc -force-instr-ref-livedebugvalues=1 -O0 -dwarf-version=5 -debugger-tune=lldb -filetype=obj < %s \
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; RUN: | llvm-dwarfdump - | FileCheck --implicit-check-not=DW_OP_entry_value %s
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; RUN: llc -force-instr-ref-livedebugvalues=1 -O0 -dwarf-version=5 -debugger-tune=gdb -march=x86-64 -filetype=obj < %s \
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; RUN: llc -force-instr-ref-livedebugvalues=1 -O0 -dwarf-version=5 -debugger-tune=gdb -filetype=obj < %s \
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; RUN: | llvm-dwarfdump - | FileCheck --implicit-check-not=DW_OP_entry_value %s
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1010
; The call-site-params are created iff corresponding DISubprogram contains

‎llvm/test/DebugInfo/X86/single-dbg_value.ll

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; RUN: llc -stop-after=livedebugvalues -o - %s \
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; RUN: | FileCheck %s --check-prefix=SANITY
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; RUN: llc -march=x86-64 -o - %s -filetype=obj \
3+
; RUN: llc -o - %s -filetype=obj \
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; RUN: | llvm-dwarfdump -v -all - | FileCheck %s
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;
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; CHECK: .debug_info contents:

‎llvm/test/Transforms/LoadStoreVectorizer/NVPTX/propagate-invariance-metadata.ll

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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2-
; RUN: opt -passes=load-store-vectorizer -march=nvptx64 -mcpu=sm_35 -S < %s | FileCheck %s
2+
; RUN: opt -passes=load-store-vectorizer -mcpu=sm_35 -S < %s | FileCheck %s
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target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64"
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target triple = "nvptx64-nvidia-cuda"

‎llvm/test/Transforms/StraightLineStrengthReduce/NVPTX/reassociate-geps-and-slsr.ll

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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
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; RUN: opt < %s -passes=separate-const-offset-from-gep,slsr,gvn -S | FileCheck %s
3-
; RUN: llc < %s -march=nvptx64 -mcpu=sm_35 | FileCheck %s --check-prefix=PTX
3+
; RUN: llc < %s -mcpu=sm_35 | FileCheck %s --check-prefix=PTX
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target datalayout = "e-i64:64-v16:16-v32:32-n16:32:64"
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target triple = "nvptx64-unknown-unknown"

‎llvm/test/Transforms/StraightLineStrengthReduce/NVPTX/speculative-slsr.ll

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; RUN: llc < %s -march=nvptx64 -mcpu=sm_35 | FileCheck %s
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; RUN: llc < %s -mcpu=sm_35 | FileCheck %s
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target datalayout = "e-i64:64-v16:16-v32:32-n16:32:64"
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target triple = "nvptx64-nvidia-cuda"

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