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[RISCV][GISel] Suppport G_BSWAP with Zbb.
1 parent 1c68c4c commit 1343d96

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5 files changed

+256
-142
lines changed

5 files changed

+256
-142
lines changed

‎llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp

Lines changed: 7 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -96,9 +96,13 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
9696

9797
getActionDefinitionsBuilder({G_ROTL, G_ROTR}).lower();
9898

99-
getActionDefinitionsBuilder({G_BSWAP, G_BITREVERSE})
100-
.maxScalar(0, sXLen)
101-
.lower();
99+
getActionDefinitionsBuilder(G_BITREVERSE).maxScalar(0, sXLen).lower();
100+
101+
auto &BSwap = getActionDefinitionsBuilder(G_BSWAP);
102+
if (ST.hasStdExtZbb())
103+
BSwap.legalFor({sXLen}).clampScalar(0, sXLen, sXLen);
104+
else
105+
BSwap.maxScalar(0, sXLen).lower();
102106

103107
getActionDefinitionsBuilder(
104108
{G_CTPOP, G_CTLZ, G_CTLZ_ZERO_UNDEF, G_CTTZ, G_CTTZ_ZERO_UNDEF})

‎llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/bswap-rv32.mir

Lines changed: 22 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,22 @@
1+
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2+
# RUN: llc -mtriple=riscv32 -mattr=+zbb -run-pass=instruction-select \
3+
# RUN: -simplify-mir -verify-machineinstrs %s -o - \
4+
# RUN: | FileCheck -check-prefix=RV32I %s
5+
6+
---
7+
name: bswap_s32
8+
legalized: true
9+
regBankSelected: true
10+
body: |
11+
bb.0.entry:
12+
; RV32I-LABEL: name: bswap_s32
13+
; RV32I: [[COPY:%[0-9]+]]:gpr = COPY $x10
14+
; RV32I-NEXT: [[REV8_RV32_:%[0-9]+]]:gpr = REV8_RV32 [[COPY]]
15+
; RV32I-NEXT: $x10 = COPY [[REV8_RV32_]]
16+
; RV32I-NEXT: PseudoRET implicit $x10
17+
%0:gprb(s32) = COPY $x10
18+
%1:gprb(s32) = G_BSWAP %0
19+
$x10 = COPY %1(s32)
20+
PseudoRET implicit $x10
21+
22+
...

‎llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/bswap-rv64.mir

Lines changed: 22 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,22 @@
1+
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2+
# RUN: llc -mtriple=riscv64 -mattr=+zbb -run-pass=instruction-select \
3+
# RUN: -simplify-mir -verify-machineinstrs %s -o - \
4+
# RUN: | FileCheck -check-prefix=RV64I %s
5+
6+
---
7+
name: bswap_s64
8+
legalized: true
9+
regBankSelected: true
10+
body: |
11+
bb.0.entry:
12+
; RV64I-LABEL: name: bswap_s64
13+
; RV64I: [[COPY:%[0-9]+]]:gpr = COPY $x10
14+
; RV64I-NEXT: [[REV8_RV64_:%[0-9]+]]:gpr = REV8_RV64 [[COPY]]
15+
; RV64I-NEXT: $x10 = COPY [[REV8_RV64_]]
16+
; RV64I-NEXT: PseudoRET implicit $x10
17+
%0:gprb(s64) = COPY $x10
18+
%1:gprb(s64) = G_BSWAP %0
19+
$x10 = COPY %1(s64)
20+
PseudoRET implicit $x10
21+
22+
...

‎llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-bswap-rv32.mir

Lines changed: 97 additions & 64 deletions
Original file line numberDiff line numberDiff line change
@@ -1,24 +1,38 @@
11
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
2-
# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - | FileCheck %s
2+
# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - \
3+
# RUN: | FileCheck %s --check-prefix=RV32I
4+
# RUN: llc -mtriple=riscv32 -mattr=+zbb -run-pass=legalizer %s -o - \
5+
# RUN: | FileCheck %s --check-prefix=RV32ZBB
36

47
---
58
name: bswap_i16
69
body: |
710
bb.0:
811
liveins: $x10
9-
; CHECK-LABEL: name: bswap_i16
10-
; CHECK: liveins: $x10
11-
; CHECK-NEXT: {{ $}}
12-
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
13-
; CHECK-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY]], 16
14-
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
15-
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ASSERT_ZEXT]], [[C]](s32)
16-
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[ASSERT_ZEXT]], [[C]](s32)
17-
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL]]
18-
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
19-
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[OR]], [[C1]]
20-
; CHECK-NEXT: $x10 = COPY [[AND]](s32)
21-
; CHECK-NEXT: PseudoRET implicit $x10
12+
; RV32I-LABEL: name: bswap_i16
13+
; RV32I: liveins: $x10
14+
; RV32I-NEXT: {{ $}}
15+
; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
16+
; RV32I-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY]], 16
17+
; RV32I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
18+
; RV32I-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ASSERT_ZEXT]], [[C]](s32)
19+
; RV32I-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[ASSERT_ZEXT]], [[C]](s32)
20+
; RV32I-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL]]
21+
; RV32I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
22+
; RV32I-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[OR]], [[C1]]
23+
; RV32I-NEXT: $x10 = COPY [[AND]](s32)
24+
; RV32I-NEXT: PseudoRET implicit $x10
25+
;
26+
; RV32ZBB-LABEL: name: bswap_i16
27+
; RV32ZBB: liveins: $x10
28+
; RV32ZBB-NEXT: {{ $}}
29+
; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
30+
; RV32ZBB-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY]], 16
31+
; RV32ZBB-NEXT: [[BSWAP:%[0-9]+]]:_(s32) = G_BSWAP [[ASSERT_ZEXT]]
32+
; RV32ZBB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
33+
; RV32ZBB-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BSWAP]], [[C]](s32)
34+
; RV32ZBB-NEXT: $x10 = COPY [[LSHR]](s32)
35+
; RV32ZBB-NEXT: PseudoRET implicit $x10
2236
%0:_(s32) = COPY $x10
2337
%1:_(s32) = G_ASSERT_ZEXT %0, 16
2438
%2:_(s16) = G_TRUNC %1(s32)
@@ -32,24 +46,32 @@ name: bswap_i32
3246
body: |
3347
bb.0:
3448
liveins: $x10
35-
; CHECK-LABEL: name: bswap_i32
36-
; CHECK: liveins: $x10
37-
; CHECK-NEXT: {{ $}}
38-
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
39-
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
40-
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
41-
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
42-
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL]]
43-
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65280
44-
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
45-
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
46-
; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C2]](s32)
47-
; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
48-
; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C2]](s32)
49-
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
50-
; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[AND1]]
51-
; CHECK-NEXT: $x10 = COPY [[OR2]](s32)
52-
; CHECK-NEXT: PseudoRET implicit $x10
49+
; RV32I-LABEL: name: bswap_i32
50+
; RV32I: liveins: $x10
51+
; RV32I-NEXT: {{ $}}
52+
; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
53+
; RV32I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
54+
; RV32I-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
55+
; RV32I-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
56+
; RV32I-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL]]
57+
; RV32I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65280
58+
; RV32I-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
59+
; RV32I-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
60+
; RV32I-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C2]](s32)
61+
; RV32I-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
62+
; RV32I-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C2]](s32)
63+
; RV32I-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
64+
; RV32I-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[AND1]]
65+
; RV32I-NEXT: $x10 = COPY [[OR2]](s32)
66+
; RV32I-NEXT: PseudoRET implicit $x10
67+
;
68+
; RV32ZBB-LABEL: name: bswap_i32
69+
; RV32ZBB: liveins: $x10
70+
; RV32ZBB-NEXT: {{ $}}
71+
; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
72+
; RV32ZBB-NEXT: [[BSWAP:%[0-9]+]]:_(s32) = G_BSWAP [[COPY]]
73+
; RV32ZBB-NEXT: $x10 = COPY [[BSWAP]](s32)
74+
; RV32ZBB-NEXT: PseudoRET implicit $x10
5375
%0:_(s32) = COPY $x10
5476
%1:_(s32) = G_BSWAP %0
5577
$x10 = COPY %1(s32)
@@ -60,38 +82,49 @@ name: bswap_i64
6082
body: |
6183
bb.0:
6284
liveins: $x10, $x11
63-
; CHECK-LABEL: name: bswap_i64
64-
; CHECK: liveins: $x10, $x11
65-
; CHECK-NEXT: {{ $}}
66-
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
67-
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
68-
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
69-
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
70-
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C]](s32)
71-
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL]]
72-
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65280
73-
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
74-
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
75-
; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C2]](s32)
76-
; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
77-
; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s32)
78-
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
79-
; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[AND1]]
80-
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
81-
; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C3]](s32)
82-
; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C3]](s32)
83-
; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s32) = G_OR [[LSHR2]], [[SHL2]]
84-
; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 65280
85-
; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
86-
; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C4]]
87-
; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
88-
; CHECK-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL3]]
89-
; CHECK-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C5]](s32)
90-
; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C4]]
91-
; CHECK-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[AND3]]
92-
; CHECK-NEXT: $x10 = COPY [[OR2]](s32)
93-
; CHECK-NEXT: $x11 = COPY [[OR5]](s32)
94-
; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11
85+
; RV32I-LABEL: name: bswap_i64
86+
; RV32I: liveins: $x10, $x11
87+
; RV32I-NEXT: {{ $}}
88+
; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
89+
; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
90+
; RV32I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
91+
; RV32I-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
92+
; RV32I-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C]](s32)
93+
; RV32I-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL]]
94+
; RV32I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65280
95+
; RV32I-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
96+
; RV32I-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
97+
; RV32I-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C2]](s32)
98+
; RV32I-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
99+
; RV32I-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s32)
100+
; RV32I-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
101+
; RV32I-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[AND1]]
102+
; RV32I-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
103+
; RV32I-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C3]](s32)
104+
; RV32I-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C3]](s32)
105+
; RV32I-NEXT: [[OR3:%[0-9]+]]:_(s32) = G_OR [[LSHR2]], [[SHL2]]
106+
; RV32I-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 65280
107+
; RV32I-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
108+
; RV32I-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C4]]
109+
; RV32I-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
110+
; RV32I-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL3]]
111+
; RV32I-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C5]](s32)
112+
; RV32I-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C4]]
113+
; RV32I-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[AND3]]
114+
; RV32I-NEXT: $x10 = COPY [[OR2]](s32)
115+
; RV32I-NEXT: $x11 = COPY [[OR5]](s32)
116+
; RV32I-NEXT: PseudoRET implicit $x10, implicit $x11
117+
;
118+
; RV32ZBB-LABEL: name: bswap_i64
119+
; RV32ZBB: liveins: $x10, $x11
120+
; RV32ZBB-NEXT: {{ $}}
121+
; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
122+
; RV32ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
123+
; RV32ZBB-NEXT: [[BSWAP:%[0-9]+]]:_(s32) = G_BSWAP [[COPY1]]
124+
; RV32ZBB-NEXT: [[BSWAP1:%[0-9]+]]:_(s32) = G_BSWAP [[COPY]]
125+
; RV32ZBB-NEXT: $x10 = COPY [[BSWAP]](s32)
126+
; RV32ZBB-NEXT: $x11 = COPY [[BSWAP1]](s32)
127+
; RV32ZBB-NEXT: PseudoRET implicit $x10, implicit $x11
95128
%0:_(s32) = COPY $x10
96129
%1:_(s32) = COPY $x11
97130
%2:_(s64) = G_MERGE_VALUES %0(s32), %1(s32)

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