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krzysz00krzysz00
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Pre-commit AMDGPU tests for masked load/store/scatter/gather (#104645)
I'm planning to fix the masked operation scalarazer to not generate suboptimal code on AMD GPUs and other SIMT machines, and so am adding tests now.
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‎llvm/test/Transforms/ScalarizeMaskedMemIntrin/AMDGPU/expamd-masked-load.ll

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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
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; RUN: opt -S %s -passes=scalarize-masked-mem-intrin -mtriple=amdgcn-amd-amdhsa | FileCheck %s
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; COM: Test that, unlike on CPU targets, the mask doesn't get bitcast to a scalar,
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; COM: since, on GPUs, each i1 takes up at least one register and so they should
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; COM: be treated separately.
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define <2 x i32> @scalarize_v2i32(ptr %p, <2 x i1> %mask, <2 x i32> %passthru) {
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; CHECK-LABEL: define <2 x i32> @scalarize_v2i32(
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; CHECK-SAME: ptr [[P:%.*]], <2 x i1> [[MASK:%.*]], <2 x i32> [[PASSTHRU:%.*]]) {
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; CHECK-NEXT: [[SCALAR_MASK:%.*]] = bitcast <2 x i1> [[MASK]] to i2
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; CHECK-NEXT: [[TMP1:%.*]] = and i2 [[SCALAR_MASK]], 1
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; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i2 [[TMP1]], 0
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; CHECK-NEXT: br i1 [[TMP2]], label %[[COND_LOAD:.*]], label %[[ELSE:.*]]
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; CHECK: [[COND_LOAD]]:
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; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[P]], i32 0
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; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
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; CHECK-NEXT: [[TMP5:%.*]] = insertelement <2 x i32> [[PASSTHRU]], i32 [[TMP4]], i64 0
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; CHECK-NEXT: br label %[[ELSE]]
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; CHECK: [[ELSE]]:
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; CHECK-NEXT: [[RES_PHI_ELSE:%.*]] = phi <2 x i32> [ [[TMP5]], %[[COND_LOAD]] ], [ [[PASSTHRU]], [[TMP0:%.*]] ]
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; CHECK-NEXT: [[TMP6:%.*]] = and i2 [[SCALAR_MASK]], -2
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; CHECK-NEXT: [[TMP7:%.*]] = icmp ne i2 [[TMP6]], 0
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; CHECK-NEXT: br i1 [[TMP7]], label %[[COND_LOAD1:.*]], label %[[ELSE2:.*]]
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; CHECK: [[COND_LOAD1]]:
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; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds i32, ptr [[P]], i32 1
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; CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4
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; CHECK-NEXT: [[TMP10:%.*]] = insertelement <2 x i32> [[RES_PHI_ELSE]], i32 [[TMP9]], i64 1
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; CHECK-NEXT: br label %[[ELSE2]]
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; CHECK: [[ELSE2]]:
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; CHECK-NEXT: [[RES_PHI_ELSE3:%.*]] = phi <2 x i32> [ [[TMP10]], %[[COND_LOAD1]] ], [ [[RES_PHI_ELSE]], %[[ELSE]] ]
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; CHECK-NEXT: ret <2 x i32> [[RES_PHI_ELSE3]]
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;
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%ret = call <2 x i32> @llvm.masked.load.v2i32.p0(ptr %p, i32 128, <2 x i1> %mask, <2 x i32> %passthru)
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ret <2 x i32> %ret
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}
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define <2 x i32> @scalarize_v2i32_splat_mask(ptr %p, i1 %mask, <2 x i32> %passthrough) {
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; CHECK-LABEL: define <2 x i32> @scalarize_v2i32_splat_mask(
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; CHECK-SAME: ptr [[P:%.*]], i1 [[MASK:%.*]], <2 x i32> [[PASSTHROUGH:%.*]]) {
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; CHECK-NEXT: [[MASK_VEC:%.*]] = insertelement <2 x i1> poison, i1 [[MASK]], i32 0
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; CHECK-NEXT: [[MASK_SPLAT:%.*]] = shufflevector <2 x i1> [[MASK_VEC]], <2 x i1> poison, <2 x i32> zeroinitializer
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; CHECK-NEXT: [[MASK_SPLAT_FIRST:%.*]] = extractelement <2 x i1> [[MASK_SPLAT]], i64 0
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; CHECK-NEXT: br i1 [[MASK_SPLAT_FIRST]], label %[[COND_LOAD:.*]], label %[[BB1:.*]]
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; CHECK: [[COND_LOAD]]:
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; CHECK-NEXT: [[RET_COND_LOAD:%.*]] = load <2 x i32>, ptr [[P]], align 8
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; CHECK-NEXT: br label %[[BB1]]
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; CHECK: [[BB1]]:
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; CHECK-NEXT: [[RET:%.*]] = phi <2 x i32> [ [[RET_COND_LOAD]], %[[COND_LOAD]] ], [ [[PASSTHROUGH]], [[TMP0:%.*]] ]
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; CHECK-NEXT: ret <2 x i32> [[RET]]
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;
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%mask.vec = insertelement <2 x i1> poison, i1 %mask, i32 0
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%mask.splat = shufflevector <2 x i1> %mask.vec, <2 x i1> poison, <2 x i32> zeroinitializer
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%ret = call <2 x i32> @llvm.masked.load.v2i32.p0(ptr %p, i32 8, <2 x i1> %mask.splat, <2 x i32> %passthrough)
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ret <2 x i32> %ret
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}
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define <2 x half> @scalarize_v2f16(ptr %p, <2 x i1> %mask, <2 x half> %passthru) {
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; CHECK-LABEL: define <2 x half> @scalarize_v2f16(
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; CHECK-SAME: ptr [[P:%.*]], <2 x i1> [[MASK:%.*]], <2 x half> [[PASSTHRU:%.*]]) {
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; CHECK-NEXT: [[SCALAR_MASK:%.*]] = bitcast <2 x i1> [[MASK]] to i2
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; CHECK-NEXT: [[TMP1:%.*]] = and i2 [[SCALAR_MASK]], 1
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; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i2 [[TMP1]], 0
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; CHECK-NEXT: br i1 [[TMP2]], label %[[COND_LOAD:.*]], label %[[ELSE:.*]]
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; CHECK: [[COND_LOAD]]:
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; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds half, ptr [[P]], i32 0
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; CHECK-NEXT: [[TMP4:%.*]] = load half, ptr [[TMP3]], align 2
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; CHECK-NEXT: [[TMP5:%.*]] = insertelement <2 x half> [[PASSTHRU]], half [[TMP4]], i64 0
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; CHECK-NEXT: br label %[[ELSE]]
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; CHECK: [[ELSE]]:
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; CHECK-NEXT: [[RES_PHI_ELSE:%.*]] = phi <2 x half> [ [[TMP5]], %[[COND_LOAD]] ], [ [[PASSTHRU]], [[TMP0:%.*]] ]
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; CHECK-NEXT: [[TMP6:%.*]] = and i2 [[SCALAR_MASK]], -2
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; CHECK-NEXT: [[TMP7:%.*]] = icmp ne i2 [[TMP6]], 0
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; CHECK-NEXT: br i1 [[TMP7]], label %[[COND_LOAD1:.*]], label %[[ELSE2:.*]]
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; CHECK: [[COND_LOAD1]]:
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; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds half, ptr [[P]], i32 1
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; CHECK-NEXT: [[TMP9:%.*]] = load half, ptr [[TMP8]], align 2
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; CHECK-NEXT: [[TMP10:%.*]] = insertelement <2 x half> [[RES_PHI_ELSE]], half [[TMP9]], i64 1
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; CHECK-NEXT: br label %[[ELSE2]]
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; CHECK: [[ELSE2]]:
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; CHECK-NEXT: [[RES_PHI_ELSE3:%.*]] = phi <2 x half> [ [[TMP10]], %[[COND_LOAD1]] ], [ [[RES_PHI_ELSE]], %[[ELSE]] ]
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; CHECK-NEXT: ret <2 x half> [[RES_PHI_ELSE3]]
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;
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%ret = call <2 x half> @llvm.masked.load.v2f16.p0(ptr %p, i32 128, <2 x i1> %mask, <2 x half> %passthru)
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ret <2 x half> %ret
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}
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define <2 x i32> @scalarize_v2i32_p3(ptr addrspace(3) %p, <2 x i1> %mask, <2 x i32> %passthru) {
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; CHECK-LABEL: define <2 x i32> @scalarize_v2i32_p3(
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; CHECK-SAME: ptr addrspace(3) [[P:%.*]], <2 x i1> [[MASK:%.*]], <2 x i32> [[PASSTHRU:%.*]]) {
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; CHECK-NEXT: [[SCALAR_MASK:%.*]] = bitcast <2 x i1> [[MASK]] to i2
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; CHECK-NEXT: [[TMP1:%.*]] = and i2 [[SCALAR_MASK]], 1
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; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i2 [[TMP1]], 0
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; CHECK-NEXT: br i1 [[TMP2]], label %[[COND_LOAD:.*]], label %[[ELSE:.*]]
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; CHECK: [[COND_LOAD]]:
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; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr addrspace(3) [[P]], i32 0
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; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr addrspace(3) [[TMP3]], align 4
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; CHECK-NEXT: [[TMP5:%.*]] = insertelement <2 x i32> [[PASSTHRU]], i32 [[TMP4]], i64 0
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; CHECK-NEXT: br label %[[ELSE]]
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; CHECK: [[ELSE]]:
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; CHECK-NEXT: [[RES_PHI_ELSE:%.*]] = phi <2 x i32> [ [[TMP5]], %[[COND_LOAD]] ], [ [[PASSTHRU]], [[TMP0:%.*]] ]
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; CHECK-NEXT: [[TMP6:%.*]] = and i2 [[SCALAR_MASK]], -2
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; CHECK-NEXT: [[TMP7:%.*]] = icmp ne i2 [[TMP6]], 0
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; CHECK-NEXT: br i1 [[TMP7]], label %[[COND_LOAD1:.*]], label %[[ELSE2:.*]]
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; CHECK: [[COND_LOAD1]]:
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; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds i32, ptr addrspace(3) [[P]], i32 1
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; CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr addrspace(3) [[TMP8]], align 4
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; CHECK-NEXT: [[TMP10:%.*]] = insertelement <2 x i32> [[RES_PHI_ELSE]], i32 [[TMP9]], i64 1
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; CHECK-NEXT: br label %[[ELSE2]]
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; CHECK: [[ELSE2]]:
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; CHECK-NEXT: [[RES_PHI_ELSE3:%.*]] = phi <2 x i32> [ [[TMP10]], %[[COND_LOAD1]] ], [ [[RES_PHI_ELSE]], %[[ELSE]] ]
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; CHECK-NEXT: ret <2 x i32> [[RES_PHI_ELSE3]]
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;
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%ret = call <2 x i32> @llvm.masked.load.v2i32.p3(ptr addrspace(3) %p, i32 128, <2 x i1> %mask, <2 x i32> %passthru)
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ret <2 x i32> %ret
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}
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define <2 x i32> @scalarize_v2i32_lane_mask(ptr %p, <2 x i32> %passthrough) {
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; CHECK-LABEL: define <2 x i32> @scalarize_v2i32_lane_mask(
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; CHECK-SAME: ptr [[P:%.*]], <2 x i32> [[PASSTHROUGH:%.*]]) {
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; CHECK-NEXT: [[ITEM_ID:%.*]] = call i32 @llvm.amdgcn.workitem.id.x()
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; CHECK-NEXT: [[MASK:%.*]] = icmp ult i32 [[ITEM_ID]], 16
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; CHECK-NEXT: [[MASK_VEC:%.*]] = insertelement <2 x i1> poison, i1 [[MASK]], i32 0
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; CHECK-NEXT: [[MASK_SPLAT:%.*]] = shufflevector <2 x i1> [[MASK_VEC]], <2 x i1> poison, <2 x i32> zeroinitializer
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; CHECK-NEXT: [[MASK_SPLAT_FIRST:%.*]] = extractelement <2 x i1> [[MASK_SPLAT]], i64 0
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; CHECK-NEXT: br i1 [[MASK_SPLAT_FIRST]], label %[[COND_LOAD:.*]], label %[[BB1:.*]]
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; CHECK: [[COND_LOAD]]:
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; CHECK-NEXT: [[RET_COND_LOAD:%.*]] = load <2 x i32>, ptr [[P]], align 8
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; CHECK-NEXT: br label %[[BB1]]
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; CHECK: [[BB1]]:
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; CHECK-NEXT: [[RET:%.*]] = phi <2 x i32> [ [[RET_COND_LOAD]], %[[COND_LOAD]] ], [ [[PASSTHROUGH]], [[TMP0:%.*]] ]
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; CHECK-NEXT: ret <2 x i32> [[RET]]
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;
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%item.id = call i32 @llvm.amdgcn.workitem.id.x()
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%mask = icmp ult i32 %item.id, 16
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%mask.vec = insertelement <2 x i1> poison, i1 %mask, i32 0
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%mask.splat = shufflevector <2 x i1> %mask.vec, <2 x i1> poison, <2 x i32> zeroinitializer
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%ret = call <2 x i32> @llvm.masked.load.v2i32.p0(ptr %p, i32 8, <2 x i1> %mask.splat, <2 x i32> %passthrough)
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ret <2 x i32> %ret
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}
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define <2 x i32> @scalarize_v2i32_group_mask(ptr %p, <2 x i32> %passthrough) {
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; CHECK-LABEL: define <2 x i32> @scalarize_v2i32_group_mask(
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; CHECK-SAME: ptr [[P:%.*]], <2 x i32> [[PASSTHROUGH:%.*]]) {
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; CHECK-NEXT: [[GROUP_ID:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x()
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; CHECK-NEXT: [[MASK:%.*]] = icmp ult i32 [[GROUP_ID]], 4
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; CHECK-NEXT: [[MASK_VEC:%.*]] = insertelement <2 x i1> poison, i1 [[MASK]], i32 0
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; CHECK-NEXT: [[MASK_SPLAT:%.*]] = shufflevector <2 x i1> [[MASK_VEC]], <2 x i1> poison, <2 x i32> zeroinitializer
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; CHECK-NEXT: [[MASK_SPLAT_FIRST:%.*]] = extractelement <2 x i1> [[MASK_SPLAT]], i64 0
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; CHECK-NEXT: br i1 [[MASK_SPLAT_FIRST]], label %[[COND_LOAD:.*]], label %[[BB1:.*]]
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; CHECK: [[COND_LOAD]]:
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; CHECK-NEXT: [[RET_COND_LOAD:%.*]] = load <2 x i32>, ptr [[P]], align 8
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; CHECK-NEXT: br label %[[BB1]]
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; CHECK: [[BB1]]:
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; CHECK-NEXT: [[RET:%.*]] = phi <2 x i32> [ [[RET_COND_LOAD]], %[[COND_LOAD]] ], [ [[PASSTHROUGH]], [[TMP0:%.*]] ]
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; CHECK-NEXT: ret <2 x i32> [[RET]]
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;
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%group.id = call i32 @llvm.amdgcn.workgroup.id.x()
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%mask = icmp ult i32 %group.id, 4
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%mask.vec = insertelement <2 x i1> poison, i1 %mask, i32 0
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%mask.splat = shufflevector <2 x i1> %mask.vec, <2 x i1> poison, <2 x i32> zeroinitializer
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%ret = call <2 x i32> @llvm.masked.load.v2i32.p0(ptr %p, i32 8, <2 x i1> %mask.splat, <2 x i32> %passthrough)
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ret <2 x i32> %ret
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}
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declare <2 x i32> @llvm.masked.load.v2i32.p0(ptr, i32, <2 x i1>, <2 x i32>)
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declare <2 x half> @llvm.masked.load.v2f16.p0(ptr, i32, <2 x i1>, <2 x half>)
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declare <2 x i32> @llvm.masked.load.v2i32.p3(ptr addrspace(3), i32, <2 x i1>, <2 x i32>)
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declare noundef i32 @llvm.amdgcn.workitem.id.x()
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declare noundef i32 @llvm.amdgcn.workgroup.id.x()

‎llvm/test/Transforms/ScalarizeMaskedMemIntrin/AMDGPU/expand-masked-gather.ll

Lines changed: 38 additions & 0 deletions
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
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; RUN: opt -S %s -passes=scalarize-masked-mem-intrin -mtriple=amdgcn-amd-amdhsa | FileCheck %s
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; COM: Test that, unlike on CPU targets, the mask doesn't get bitcast to a scalar,
5+
; COM: since, on GPUs, each i1 takes up at least one register and so they should
6+
; COM: be treated separately.
7+
8+
define <2 x i32> @scalarize_v2i32(<2 x ptr> %p, <2 x i1> %mask, <2 x i32> %passthru) {
9+
; CHECK-LABEL: define <2 x i32> @scalarize_v2i32(
10+
; CHECK-SAME: <2 x ptr> [[P:%.*]], <2 x i1> [[MASK:%.*]], <2 x i32> [[PASSTHRU:%.*]]) {
11+
; CHECK-NEXT: [[SCALAR_MASK:%.*]] = bitcast <2 x i1> [[MASK]] to i2
12+
; CHECK-NEXT: [[TMP1:%.*]] = and i2 [[SCALAR_MASK]], 1
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; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i2 [[TMP1]], 0
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; CHECK-NEXT: br i1 [[TMP2]], label %[[COND_LOAD:.*]], label %[[ELSE:.*]]
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; CHECK: [[COND_LOAD]]:
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; CHECK-NEXT: [[PTR0:%.*]] = extractelement <2 x ptr> [[P]], i64 0
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; CHECK-NEXT: [[LOAD0:%.*]] = load i32, ptr [[PTR0]], align 8
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; CHECK-NEXT: [[RES0:%.*]] = insertelement <2 x i32> [[PASSTHRU]], i32 [[LOAD0]], i64 0
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; CHECK-NEXT: br label %[[ELSE]]
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; CHECK: [[ELSE]]:
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; CHECK-NEXT: [[RES_PHI_ELSE:%.*]] = phi <2 x i32> [ [[RES0]], %[[COND_LOAD]] ], [ [[PASSTHRU]], [[TMP0:%.*]] ]
22+
; CHECK-NEXT: [[TMP3:%.*]] = and i2 [[SCALAR_MASK]], -2
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; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i2 [[TMP3]], 0
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; CHECK-NEXT: br i1 [[TMP4]], label %[[COND_LOAD1:.*]], label %[[ELSE2:.*]]
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; CHECK: [[COND_LOAD1]]:
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; CHECK-NEXT: [[PTR1:%.*]] = extractelement <2 x ptr> [[P]], i64 1
27+
; CHECK-NEXT: [[LOAD1:%.*]] = load i32, ptr [[PTR1]], align 8
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; CHECK-NEXT: [[RES1:%.*]] = insertelement <2 x i32> [[RES_PHI_ELSE]], i32 [[LOAD1]], i64 1
29+
; CHECK-NEXT: br label %[[ELSE2]]
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; CHECK: [[ELSE2]]:
31+
; CHECK-NEXT: [[RES_PHI_ELSE3:%.*]] = phi <2 x i32> [ [[RES1]], %[[COND_LOAD1]] ], [ [[RES_PHI_ELSE]], %[[ELSE]] ]
32+
; CHECK-NEXT: ret <2 x i32> [[RES_PHI_ELSE3]]
33+
;
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%ret = call <2 x i32> @llvm.masked.gather.v2i32.v2p0(<2 x ptr> %p, i32 8, <2 x i1> %mask, <2 x i32> %passthru)
35+
ret <2 x i32> %ret
36+
}
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declare <2 x i32> @llvm.masked.gather.v2i32.v2p0(<2 x ptr>, i32, <2 x i1>, <2 x i32>)

‎llvm/test/Transforms/ScalarizeMaskedMemIntrin/AMDGPU/expand-masked-scatter.ll

Lines changed: 36 additions & 0 deletions
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@@ -0,0 +1,36 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
2+
; RUN: opt -S %s -passes=scalarize-masked-mem-intrin -mtriple=amdgcn-amd-amdhsa | FileCheck %s
3+
4+
; COM: Test that, unlike on CPU targets, the mask doesn't get bitcast to a scalar,
5+
; COM: since, on GPUs, each i1 takes up at least one register and so they should
6+
; COM: be treated separately.
7+
8+
define void @scalarize_v2i32(<2 x ptr> %p, <2 x i1> %mask, <2 x i32> %value) {
9+
; CHECK-LABEL: define void @scalarize_v2i32(
10+
; CHECK-SAME: <2 x ptr> [[P:%.*]], <2 x i1> [[MASK:%.*]], <2 x i32> [[VALUE:%.*]]) {
11+
; CHECK-NEXT: [[SCALAR_MASK:%.*]] = bitcast <2 x i1> [[MASK]] to i2
12+
; CHECK-NEXT: [[TMP1:%.*]] = and i2 [[SCALAR_MASK]], 1
13+
; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i2 [[TMP1]], 0
14+
; CHECK-NEXT: br i1 [[TMP2]], label %[[COND_STORE:.*]], label %[[ELSE:.*]]
15+
; CHECK: [[COND_STORE]]:
16+
; CHECK-NEXT: [[ELT0:%.*]] = extractelement <2 x i32> [[VALUE]], i64 0
17+
; CHECK-NEXT: [[PTR0:%.*]] = extractelement <2 x ptr> [[P]], i64 0
18+
; CHECK-NEXT: store i32 [[ELT0]], ptr [[PTR0]], align 8
19+
; CHECK-NEXT: br label %[[ELSE]]
20+
; CHECK: [[ELSE]]:
21+
; CHECK-NEXT: [[TMP3:%.*]] = and i2 [[SCALAR_MASK]], -2
22+
; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i2 [[TMP3]], 0
23+
; CHECK-NEXT: br i1 [[TMP4]], label %[[COND_STORE1:.*]], label %[[ELSE2:.*]]
24+
; CHECK: [[COND_STORE1]]:
25+
; CHECK-NEXT: [[ELT1:%.*]] = extractelement <2 x i32> [[VALUE]], i64 1
26+
; CHECK-NEXT: [[PTR1:%.*]] = extractelement <2 x ptr> [[P]], i64 1
27+
; CHECK-NEXT: store i32 [[ELT1]], ptr [[PTR1]], align 8
28+
; CHECK-NEXT: br label %[[ELSE2]]
29+
; CHECK: [[ELSE2]]:
30+
; CHECK-NEXT: ret void
31+
;
32+
call void @llvm.masked.scatter.v2i32.v2p0(<2 x i32> %value, <2 x ptr> %p, i32 8, <2 x i1> %mask)
33+
ret void
34+
}
35+
36+
declare void @llvm.masked.scatter.v2i32.v2p0(<2 x i32>, <2 x ptr>, i32, <2 x i1>)

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