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[clang][RISCV] Enable RVV with function attribute __attribute__((target("arch=+v"))) (#83674)
It is currently not possible to use "RVV type" and "RVV intrinsics" if the "zve32x" is not enabled globally. However in some cases we may want to use them only in some functions, for instance: ``` #include <riscv_vector.h> __attribute__((target("+zve32x"))) vint32m1_t rvv_add(vint32m1_t v1, vint32m1_t v2, size_t vl) { return __riscv_vadd(v1, v2, vl); } int other_add(int i1, int i2) { return i1 + i2; } ``` , it is supposed to be compilable even the vector is not specified, e.g. `clang -target riscv64 -march=rv64gc -S test.c`.
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‎clang/include/clang/Sema/Sema.h

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2234,7 +2234,8 @@ class Sema final {
22342234
bool CheckRISCVLMUL(CallExpr *TheCall, unsigned ArgNum);
22352235
bool CheckRISCVBuiltinFunctionCall(const TargetInfo &TI, unsigned BuiltinID,
22362236
CallExpr *TheCall);
2237-
void checkRVVTypeSupport(QualType Ty, SourceLocation Loc, Decl *D);
2237+
void checkRVVTypeSupport(QualType Ty, SourceLocation Loc, Decl *D,
2238+
const llvm::StringMap<bool> &FeatureMap);
22382239
bool CheckLoongArchBuiltinFunctionCall(const TargetInfo &TI,
22392240
unsigned BuiltinID, CallExpr *TheCall);
22402241
bool CheckWebAssemblyBuiltinFunctionCall(const TargetInfo &TI,

‎clang/lib/Sema/Sema.cpp

Lines changed: 5 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2065,8 +2065,11 @@ void Sema::checkTypeSupport(QualType Ty, SourceLocation Loc, ValueDecl *D) {
20652065
targetDiag(D->getLocation(), diag::note_defined_here, FD) << D;
20662066
}
20672067

2068-
if (TI.hasRISCVVTypes() && Ty->isRVVSizelessBuiltinType())
2069-
checkRVVTypeSupport(Ty, Loc, D);
2068+
if (TI.hasRISCVVTypes() && Ty->isRVVSizelessBuiltinType() && FD) {
2069+
llvm::StringMap<bool> CallerFeatureMap;
2070+
Context.getFunctionFeatureMap(CallerFeatureMap, FD);
2071+
checkRVVTypeSupport(Ty, Loc, D, CallerFeatureMap);
2072+
}
20702073

20712074
// Don't allow SVE types in functions without a SVE target.
20722075
if (Ty->isSVESizelessBuiltinType() && FD && FD->hasBody()) {

‎clang/lib/Sema/SemaChecking.cpp

Lines changed: 9 additions & 61 deletions
Original file line numberDiff line numberDiff line change
@@ -5760,57 +5760,6 @@ static bool CheckInvalidVLENandLMUL(const TargetInfo &TI, CallExpr *TheCall,
57605760
bool Sema::CheckRISCVBuiltinFunctionCall(const TargetInfo &TI,
57615761
unsigned BuiltinID,
57625762
CallExpr *TheCall) {
5763-
// CodeGenFunction can also detect this, but this gives a better error
5764-
// message.
5765-
bool FeatureMissing = false;
5766-
SmallVector<StringRef> ReqFeatures;
5767-
StringRef Features = Context.BuiltinInfo.getRequiredFeatures(BuiltinID);
5768-
Features.split(ReqFeatures, ',', -1, false);
5769-
5770-
// Check if each required feature is included
5771-
for (StringRef F : ReqFeatures) {
5772-
SmallVector<StringRef> ReqOpFeatures;
5773-
F.split(ReqOpFeatures, '|');
5774-
5775-
if (llvm::none_of(ReqOpFeatures,
5776-
[&TI](StringRef OF) { return TI.hasFeature(OF); })) {
5777-
std::string FeatureStrs;
5778-
bool IsExtension = true;
5779-
for (StringRef OF : ReqOpFeatures) {
5780-
// If the feature is 64bit, alter the string so it will print better in
5781-
// the diagnostic.
5782-
if (OF == "64bit") {
5783-
assert(ReqOpFeatures.size() == 1 && "Expected '64bit' to be alone");
5784-
OF = "RV64";
5785-
IsExtension = false;
5786-
}
5787-
if (OF == "32bit") {
5788-
assert(ReqOpFeatures.size() == 1 && "Expected '32bit' to be alone");
5789-
OF = "RV32";
5790-
IsExtension = false;
5791-
}
5792-
5793-
// Convert features like "zbr" and "experimental-zbr" to "Zbr".
5794-
OF.consume_front("experimental-");
5795-
std::string FeatureStr = OF.str();
5796-
FeatureStr[0] = std::toupper(FeatureStr[0]);
5797-
// Combine strings.
5798-
FeatureStrs += FeatureStrs.empty() ? "" : ", ";
5799-
FeatureStrs += "'";
5800-
FeatureStrs += FeatureStr;
5801-
FeatureStrs += "'";
5802-
}
5803-
// Error message
5804-
FeatureMissing = true;
5805-
Diag(TheCall->getBeginLoc(), diag::err_riscv_builtin_requires_extension)
5806-
<< IsExtension
5807-
<< TheCall->getSourceRange() << StringRef(FeatureStrs);
5808-
}
5809-
}
5810-
5811-
if (FeatureMissing)
5812-
return true;
5813-
58145763
// vmulh.vv, vmulh.vx, vmulhu.vv, vmulhu.vx, vmulhsu.vv, vmulhsu.vx,
58155764
// vsmul.vv, vsmul.vx are not included for EEW=64 in Zve64*.
58165765
switch (BuiltinID) {
@@ -6714,36 +6663,35 @@ bool Sema::CheckWebAssemblyBuiltinFunctionCall(const TargetInfo &TI,
67146663
return false;
67156664
}
67166665

6717-
void Sema::checkRVVTypeSupport(QualType Ty, SourceLocation Loc, Decl *D) {
6718-
const TargetInfo &TI = Context.getTargetInfo();
6719-
6666+
void Sema::checkRVVTypeSupport(QualType Ty, SourceLocation Loc, Decl *D,
6667+
const llvm::StringMap<bool> &FeatureMap) {
67206668
ASTContext::BuiltinVectorTypeInfo Info =
67216669
Context.getBuiltinVectorTypeInfo(Ty->castAs<BuiltinType>());
67226670
unsigned EltSize = Context.getTypeSize(Info.ElementType);
67236671
unsigned MinElts = Info.EC.getKnownMinValue();
67246672

67256673
if (Info.ElementType->isSpecificBuiltinType(BuiltinType::Double) &&
6726-
!TI.hasFeature("zve64d"))
6674+
!FeatureMap.lookup("zve64d"))
67276675
Diag(Loc, diag::err_riscv_type_requires_extension, D) << Ty << "zve64d";
67286676
// (ELEN, LMUL) pairs of (8, mf8), (16, mf4), (32, mf2), (64, m1) requires at
67296677
// least zve64x
67306678
else if (((EltSize == 64 && Info.ElementType->isIntegerType()) ||
67316679
MinElts == 1) &&
6732-
!TI.hasFeature("zve64x"))
6680+
!FeatureMap.lookup("zve64x"))
67336681
Diag(Loc, diag::err_riscv_type_requires_extension, D) << Ty << "zve64x";
6734-
else if (Info.ElementType->isFloat16Type() && !TI.hasFeature("zvfh") &&
6735-
!TI.hasFeature("zvfhmin"))
6682+
else if (Info.ElementType->isFloat16Type() && !FeatureMap.lookup("zvfh") &&
6683+
!FeatureMap.lookup("zvfhmin"))
67366684
Diag(Loc, diag::err_riscv_type_requires_extension, D)
67376685
<< Ty << "zvfh or zvfhmin";
67386686
else if (Info.ElementType->isBFloat16Type() &&
6739-
!TI.hasFeature("experimental-zvfbfmin"))
6687+
!FeatureMap.lookup("experimental-zvfbfmin"))
67406688
Diag(Loc, diag::err_riscv_type_requires_extension, D) << Ty << "zvfbfmin";
67416689
else if (Info.ElementType->isSpecificBuiltinType(BuiltinType::Float) &&
6742-
!TI.hasFeature("zve32f"))
6690+
!FeatureMap.lookup("zve32f"))
67436691
Diag(Loc, diag::err_riscv_type_requires_extension, D) << Ty << "zve32f";
67446692
// Given that caller already checked isRVVType() before calling this function,
67456693
// if we don't have at least zve32x supported, then we need to emit error.
6746-
else if (!TI.hasFeature("zve32x"))
6694+
else if (!FeatureMap.lookup("zve32x"))
67476695
Diag(Loc, diag::err_riscv_type_requires_extension, D) << Ty << "zve32x";
67486696
}
67496697

‎clang/lib/Sema/SemaDecl.cpp

Lines changed: 7 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -8962,8 +8962,13 @@ void Sema::CheckVariableDeclarationType(VarDecl *NewVD) {
89628962
}
89638963
}
89648964

8965-
if (T->isRVVSizelessBuiltinType())
8966-
checkRVVTypeSupport(T, NewVD->getLocation(), cast<Decl>(CurContext));
8965+
if (T->isRVVSizelessBuiltinType() && isa<FunctionDecl>(CurContext)) {
8966+
const FunctionDecl *FD = cast<FunctionDecl>(CurContext);
8967+
llvm::StringMap<bool> CallerFeatureMap;
8968+
Context.getFunctionFeatureMap(CallerFeatureMap, FD);
8969+
checkRVVTypeSupport(T, NewVD->getLocation(), cast<Decl>(CurContext),
8970+
CallerFeatureMap);
8971+
}
89678972
}
89688973

89698974
/// Perform semantic checking on a newly-created variable

‎clang/test/CodeGen/RISCV/riscv-func-attr-target-err.c

Lines changed: 22 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2,6 +2,28 @@
22
// RUN: not %clang_cc1 -triple riscv64 -target-feature +zifencei -target-feature +m -target-feature +a \
33
// RUN: -emit-llvm %s 2>&1 | FileCheck %s
44

5+
#include <riscv_vector.h>
6+
7+
void test_builtin() {
8+
// CHECK: error: '__builtin_rvv_vsetvli' needs target feature zve32x
9+
__riscv_vsetvl_e8m8(1);
10+
}
11+
12+
void test_rvv_i32_type() {
13+
// CHECK: error: RISC-V type 'vint32m1_t' (aka '__rvv_int32m1_t') requires the 'zve32x' extension
14+
vint32m1_t v;
15+
}
16+
17+
void test_rvv_f32_type() {
18+
// CHECK: error: RISC-V type 'vfloat32m1_t' (aka '__rvv_float32m1_t') requires the 'zve32f' extension
19+
vfloat32m1_t v;
20+
}
21+
22+
void test_rvv_f64_type() {
23+
// CHECK: error: RISC-V type 'vfloat64m1_t' (aka '__rvv_float64m1_t') requires the 'zve64d' extension
24+
vfloat64m1_t v;
25+
}
26+
527
// CHECK: error: duplicate 'arch=' in the 'target' attribute string;
628
__attribute__((target("arch=rv64gc;arch=rv64gc_zbb"))) void testMultiArchSelectLast() {}
729
// CHECK: error: duplicate 'cpu=' in the 'target' attribute string;

‎clang/test/CodeGen/RISCV/riscv-func-attr-target.c

Lines changed: 33 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -4,6 +4,8 @@
44
// RUN: -target-feature -relax -target-feature -zfa \
55
// RUN: -emit-llvm %s -o - | FileCheck %s
66

7+
#include <riscv_vector.h>
8+
79
// CHECK-LABEL: define dso_local void @testDefault
810
// CHECK-SAME: () #0 {
911
void testDefault() {}
@@ -35,6 +37,34 @@ testAttrFullArchAndAttrCpu() {}
3537
// CHECK-SAME: () #8 {
3638
__attribute__((target("cpu=sifive-u54"))) void testAttrCpuOnly() {}
3739

40+
__attribute__((target("arch=+zve32x")))
41+
void test_builtin_w_zve32x() {
42+
// CHECK-LABEL: test_builtin_w_zve32x
43+
// CHECK-SAME: #9
44+
__riscv_vsetvl_e8m8(1);
45+
}
46+
47+
__attribute__((target("arch=+zve32x")))
48+
void test_rvv_i32_type_w_zve32x() {
49+
// CHECK-LABEL: test_rvv_i32_type_w_zve32x
50+
// CHECK-SAME: #9
51+
vint32m1_t v;
52+
}
53+
54+
__attribute__((target("arch=+zve32f")))
55+
void test_rvv_f32_type_w_zve32f() {
56+
// CHECK-LABEL: test_rvv_f32_type_w_zve32f
57+
// CHECK-SAME: #11
58+
vfloat32m1_t v;
59+
}
60+
61+
__attribute__((target("arch=+zve64d")))
62+
void test_rvv_f64_type_w_zve64d() {
63+
// CHECK-LABEL: test_rvv_f64_type_w_zve64d
64+
// CHECK-SAME: #12
65+
vfloat64m1_t v;
66+
}
67+
3868
//.
3969
// CHECK: attributes #0 = { {{.*}}"target-features"="+64bit,+a,+m,+save-restore,+zifencei,-relax,-zbb,-zfa" }
4070
// CHECK: attributes #1 = { {{.*}}"target-cpu"="rocket-rv64" "target-features"="+64bit,+a,+d,+f,+m,+save-restore,+v,+zicsr,+zifencei,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-relax,-zbb,-zfa" "tune-cpu"="generic-rv64" }
@@ -46,3 +76,6 @@ __attribute__((target("cpu=sifive-u54"))) void testAttrCpuOnly() {}
4676
// CHECK: attributes #6 = { {{.*}}"target-cpu"="sifive-u54" "target-features"="+64bit,+a,+m,+save-restore,+zbb,+zifencei,-relax,-zfa" }
4777
// CHECK: attributes #7 = { {{.*}}"target-cpu"="sifive-u54" "target-features"="+64bit,+m,+save-restore,{{(-[[:alnum:]-]+)(,-[[:alnum:]-]+)*}}" }
4878
// CHECK: attributes #8 = { {{.*}}"target-cpu"="sifive-u54" "target-features"="+64bit,+a,+c,+d,+f,+m,+save-restore,+zicsr,+zifencei,{{(-[[:alnum:]-]+)(,-[[:alnum:]-]+)*}}" }
79+
// CHECK: attributes #9 = { {{.*}}"target-features"="+64bit,+a,+m,+save-restore,+zicsr,+zifencei,+zve32x,+zvl32b,-relax,-zbb,-zfa" }
80+
// CHECK: attributes #11 = { {{.*}}"target-features"="+64bit,+a,+f,+m,+save-restore,+zicsr,+zifencei,+zve32f,+zve32x,+zvl32b,-relax,-zbb,-zfa" }
81+
// CHECK: attributes #12 = { {{.*}}"target-features"="+64bit,+a,+d,+f,+m,+save-restore,+zicsr,+zifencei,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl32b,+zvl64b,-relax,-zbb,-zfa" }

‎clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb-error.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
2-
// RUN: %clang_cc1 -triple riscv32 -target-feature +zbb -verify %s -o -
2+
// RUN: %clang_cc1 -triple riscv32 -target-feature +zbb -S -verify %s -o -
33

44
unsigned int orc_b_64(unsigned int a) {
5-
return __builtin_riscv_orc_b_64(a); // expected-error {{builtin requires: 'RV64'}}
5+
return __builtin_riscv_orc_b_64(a); // expected-error {{'__builtin_riscv_orc_b_64' needs target feature zbb,64bit}}
66
}

‎clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkb-error.c

Lines changed: 4 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1,14 +1,10 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
2-
// RUN: %clang_cc1 -triple riscv64 -target-feature +zbkb -verify %s -o -
2+
// RUN: %clang_cc1 -triple riscv64 -target-feature +zbkb -S -verify %s -o -
33

44
#include <stdint.h>
55

6-
uint32_t zip(uint32_t rs1)
6+
uint32_t zip_unzip(uint32_t rs1)
77
{
8-
return __builtin_riscv_zip_32(rs1); // expected-error {{builtin requires: 'RV32'}}
9-
}
10-
11-
uint32_t unzip(uint32_t rs1)
12-
{
13-
return __builtin_riscv_unzip_32(rs1); // expected-error {{builtin requires: 'RV32'}}
8+
(void)__builtin_riscv_zip_32(rs1); // expected-error {{'__builtin_riscv_zip_32' needs target feature zbkb,32bit}}
9+
return __builtin_riscv_unzip_32(rs1); // expected-error {{'__builtin_riscv_unzip_32' needs target feature zbkb,32bit}}
1410
}

‎clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -11,7 +11,7 @@
1111
// CHECK-RV64V-NEXT: ret i32 [[CONV]]
1212
//
1313

14-
// CHECK-RV64-ERR: error: builtin requires at least one of the following extensions: 'Zve32x'
14+
// CHECK-RV64-ERR: error: '__builtin_rvv_vsetvli' needs target feature zve32x
1515

1616
int test() {
1717
return __builtin_rvv_vsetvli(1, 0, 0);

‎clang/utils/TableGen/RISCVVEmitter.cpp

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -334,10 +334,6 @@ void RVVEmitter::createHeader(raw_ostream &OS) {
334334
OS << "#include <stdint.h>\n";
335335
OS << "#include <stddef.h>\n\n";
336336

337-
OS << "#ifndef __riscv_vector\n";
338-
OS << "#error \"Vector intrinsics require the vector extension.\"\n";
339-
OS << "#endif\n\n";
340-
341337
OS << "#ifdef __cplusplus\n";
342338
OS << "extern \"C\" {\n";
343339
OS << "#endif\n\n";

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