[ScheduleDAG] Fix false assert target

clearlov7e77 · lcvon007 · commit 13c603a41f13 · 2023-09-27T16:30:16.000+08:00
In SUnit::removePred, N->WeakSuccsLeft is reduced but WeakSuccsLeft is checked. Reviewed By: kerbowa Differential Revision: https://reviews.llvm.org/D151311
diff --git a/llvm/lib/CodeGen/ScheduleDAG.cpp b/llvm/lib/CodeGen/ScheduleDAG.cpp
@@ -201,7 +201,7 @@ void SUnit::removePred(const SDep &D) {
   }
   if (!isScheduled) {
     if (D.isWeak()) {
-      assert(WeakSuccsLeft > 0 && "WeakSuccsLeft will underflow!");
+      assert(N->WeakSuccsLeft > 0 && "WeakSuccsLeft will underflow!");
       --N->WeakSuccsLeft;
     } else {
       assert(N->NumSuccsLeft > 0 && "NumSuccsLeft will underflow!");

Original file line number	Diff line number	Diff line change
`@@ -201,7 +201,7 @@ void SUnit::removePred(const SDep &D) {`
`201`	`201`	`}`
`202`	`202`	`if (!isScheduled) {`
`203`	`203`	`if (D.isWeak()) {`
`204`		`- assert(WeakSuccsLeft > 0 && "WeakSuccsLeft will underflow!");`
	`204`	`+ assert(N->WeakSuccsLeft > 0 && "WeakSuccsLeft will underflow!");`
`205`	`205`	`--N->WeakSuccsLeft;`
`206`	`206`	`} else {`
`207`	`207`	`assert(N->NumSuccsLeft > 0 && "NumSuccsLeft will underflow!");`