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1 parent f085778 commit 1427284Copy full SHA for 1427284
llvm/test/CodeGen/AMDGPU/freeze-binary.ll
@@ -12,17 +12,6 @@ define float @freeze_fneg(float %input) nounwind {
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ret float %z
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}
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-define <8 x float> @freeze_fneg_vec(<8 x float> %input) nounwind {
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-; CHECK-LABEL: freeze_fneg_vec:
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-; CHECK: ; %bb.0:
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-; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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-; CHECK-NEXT: s_setpc_b64 s[30:31]
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- %x = fneg <8 x float> %input
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- %y = freeze <8 x float> %x
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- %z = fneg <8 x float> %y
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- ret <8 x float> %z
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-}
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-
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define float @freeze_fadd(float %input) nounwind {
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; CHECK-LABEL: freeze_fadd:
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; CHECK: ; %bb.0:
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