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JonPsson1JonPsson1
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Try without CC pseudos
1 parent ce4f19f commit 1466e68

14 files changed

+167
-196
lines changed

‎llvm/lib/Target/SystemZ/CMakeLists.txt

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -20,7 +20,6 @@ add_llvm_target(SystemZCodeGen
2020
SystemZConstantPoolValue.cpp
2121
SystemZCopyPhysRegs.cpp
2222
SystemZElimCompare.cpp
23-
SystemZFinalizeReassociation.cpp
2423
SystemZFrameLowering.cpp
2524
SystemZHazardRecognizer.cpp
2625
SystemZISelDAGToDAG.cpp

‎llvm/lib/Target/SystemZ/SystemZ.h

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -195,14 +195,12 @@ FunctionPass *createSystemZShortenInstPass(SystemZTargetMachine &TM);
195195
FunctionPass *createSystemZLongBranchPass(SystemZTargetMachine &TM);
196196
FunctionPass *createSystemZLDCleanupPass(SystemZTargetMachine &TM);
197197
FunctionPass *createSystemZCopyPhysRegsPass(SystemZTargetMachine &TM);
198-
FunctionPass *createSystemZFinalizeReassociationPass(SystemZTargetMachine &TM);
199198
FunctionPass *createSystemZPostRewritePass(SystemZTargetMachine &TM);
200199
FunctionPass *createSystemZTDCPass();
201200

202201
void initializeSystemZCopyPhysRegsPass(PassRegistry &);
203202
void initializeSystemZDAGToDAGISelPass(PassRegistry &);
204203
void initializeSystemZElimComparePass(PassRegistry &);
205-
void initializeSystemZFinalizeReassociationPass(PassRegistry &);
206204
void initializeSystemZLDCleanupPass(PassRegistry &);
207205
void initializeSystemZLongBranchPass(PassRegistry &);
208206
void initializeSystemZPostRewritePass(PassRegistry &);

‎llvm/lib/Target/SystemZ/SystemZFinalizeReassociation.cpp

Lines changed: 0 additions & 96 deletions
This file was deleted.

‎llvm/lib/Target/SystemZ/SystemZInstrFormats.td

Lines changed: 0 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -5536,21 +5536,3 @@ multiclass StringRRE<string mnemonic, bits<16> opcode,
55365536
[(set GR64:$end, (operator GR64:$start1, GR64:$start2,
55375537
GR32:$char))]>;
55385538
}
5539-
5540-
// Duplicate the instruction with a pseudo that defines CC that will be
5541-
// selected in cases where reassociation is enabled. The CC operand is needed
5542-
// in order to do later reg/mem folding into instructions that clobber CC.
5543-
multiclass BinaryVRRcAndCCPseudo<string mnemonic, bits<16> opcode,
5544-
SDPatternOperator operator,
5545-
SDPatternOperator reassoc_operator,
5546-
TypedReg tr1, TypedReg tr2, bits<4> type = 0,
5547-
bits<4> m5 = 0, bits<4> m6 = 0,
5548-
string fp_mnemonic = ""> {
5549-
def "" : BinaryVRRc<mnemonic, opcode, operator, tr1, tr2, type, m5, m6,
5550-
fp_mnemonic>;
5551-
let Defs = [CC], AddedComplexity = 1 in // Win over "".
5552-
def _CCPseudo : Pseudo<(outs tr1.op:$V1), (ins tr2.op:$V2, tr2.op:$V3),
5553-
[(set (tr1.vt tr1.op:$V1),
5554-
(reassoc_operator (tr2.vt tr2.op:$V2),
5555-
(tr2.vt tr2.op:$V3)))]>;
5556-
}

‎llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp

Lines changed: 39 additions & 43 deletions
Original file line numberDiff line numberDiff line change
@@ -629,6 +629,7 @@ MachineInstr *SystemZInstrInfo::optimizeLoadInstr(MachineInstr &MI,
629629
Register &FoldAsLoadDefReg,
630630
MachineInstr *&DefMI) const {
631631
const TargetRegisterInfo *TRI = MRI->getTargetRegisterInfo();
632+
MachineBasicBlock *MBB = MI.getParent();
632633

633634
// Check whether we can move the DefMI load, and that it only has one use.
634635
DefMI = MRI->getVRegDef(FoldAsLoadDefReg);
@@ -641,31 +642,48 @@ MachineInstr *SystemZInstrInfo::optimizeLoadInstr(MachineInstr &MI,
641642
// For reassociable FP operations, any loads have been purposefully left
642643
// unfolded so that MachineCombiner can do its work on reg/reg
643644
// opcodes. After that, as many loads as possible are now folded.
645+
// TODO: This may be beneficial with other opcodes as well as machine-sink
646+
// can move loads close to their user in a different MBB.
644647
unsigned LoadOpc = 0;
645648
unsigned RegMemOpcode = 0;
646649
const TargetRegisterClass *FPRC = nullptr;
647-
RegMemOpcode = MI.getOpcode() == SystemZ::WFADB_CCPseudo ? SystemZ::ADB
648-
: MI.getOpcode() == SystemZ::WFSDB_CCPseudo ? SystemZ::SDB
649-
: MI.getOpcode() == SystemZ::WFMDB ? SystemZ::MDB
650-
: 0;
650+
RegMemOpcode = MI.getOpcode() == SystemZ::WFADB ? SystemZ::ADB
651+
: MI.getOpcode() == SystemZ::WFSDB ? SystemZ::SDB
652+
: MI.getOpcode() == SystemZ::WFMDB ? SystemZ::MDB
653+
: 0;
651654
if (RegMemOpcode) {
652655
LoadOpc = SystemZ::VL64;
653656
FPRC = &SystemZ::FP64BitRegClass;
654657
} else {
655-
RegMemOpcode = MI.getOpcode() == SystemZ::WFASB_CCPseudo ? SystemZ::AEB
656-
: MI.getOpcode() == SystemZ::WFSSB_CCPseudo ? SystemZ::SEB
657-
: MI.getOpcode() == SystemZ::WFMSB ? SystemZ::MEEB
658-
: 0;
658+
RegMemOpcode = MI.getOpcode() == SystemZ::WFASB ? SystemZ::AEB
659+
: MI.getOpcode() == SystemZ::WFSSB ? SystemZ::SEB
660+
: MI.getOpcode() == SystemZ::WFMSB ? SystemZ::MEEB
661+
: 0;
659662
if (RegMemOpcode) {
660663
LoadOpc = SystemZ::VL32;
661664
FPRC = &SystemZ::FP32BitRegClass;
662665
}
663666
}
664667
if (!RegMemOpcode || DefMI->getOpcode() != LoadOpc)
665668
return nullptr;
666-
assert((MI.findRegisterDefOperandIdx(SystemZ::CC) == -1 ||
667-
MI.findRegisterDefOperandIdx(SystemZ::CC, /*isDead=*/true) != -1) &&
668-
"Expected dead CC-def on add/sub pseudo instruction.");
669+
670+
// If RegMemOpcode clobbers CC, first make sure CC is not live at this point.
671+
if (get(RegMemOpcode).hasImplicitDefOfPhysReg(SystemZ::CC)) {
672+
assert(DefMI->getParent() == MI.getParent() && "Assuming a local fold.");
673+
for (MachineBasicBlock::iterator MII = std::prev(MI.getIterator());;
674+
--MII) {
675+
if (MII->definesRegister(SystemZ::CC)) {
676+
if (!MII->registerDefIsDead(SystemZ::CC))
677+
return nullptr;
678+
break;
679+
}
680+
if (MII == MBB->begin()) {
681+
if (MBB->isLiveIn(SystemZ::CC))
682+
return nullptr;
683+
break;
684+
}
685+
}
686+
}
669687

670688
Register DstReg = MI.getOperand(0).getReg();
671689
MachineOperand LHS = MI.getOperand(1);
@@ -1072,25 +1090,6 @@ SystemZInstrInfo::convertToThreeAddress(MachineInstr &MI, LiveVariables *LV,
10721090
return nullptr;
10731091
}
10741092

1075-
void SystemZInstrInfo::finalizeInsInstrs(
1076-
MachineInstr &Root, unsigned &P,
1077-
SmallVectorImpl<MachineInstr *> &InsInstrs) const {
1078-
const TargetRegisterInfo *TRI =
1079-
Root.getParent()->getParent()->getSubtarget().getRegisterInfo();
1080-
for (auto *Inst : InsInstrs) {
1081-
switch (Inst->getOpcode()) {
1082-
case SystemZ::WFADB_CCPseudo:
1083-
case SystemZ::WFASB_CCPseudo:
1084-
case SystemZ::WFSDB_CCPseudo:
1085-
case SystemZ::WFSSB_CCPseudo:
1086-
Inst->addRegisterDead(SystemZ::CC, TRI);
1087-
break;
1088-
default:
1089-
break;
1090-
}
1091-
}
1092-
}
1093-
10941093
bool SystemZInstrInfo::isAssociativeAndCommutative(const MachineInstr &Inst,
10951094
bool Invert) const {
10961095
unsigned Opc = Inst.getOpcode();
@@ -1105,11 +1104,8 @@ bool SystemZInstrInfo::isAssociativeAndCommutative(const MachineInstr &Inst,
11051104
default:
11061105
break;
11071106
// Adds and multiplications.
1108-
case SystemZ::WFADB_CCPseudo:
1109-
case SystemZ::WFASB_CCPseudo:
1110-
assert(Inst.findRegisterDefOperandIdx(SystemZ::CC, /*isDead=*/true) != -1 &&
1111-
"Expected dead CC-def on add/sub pseudo instruction.");
1112-
LLVM_FALLTHROUGH;
1107+
case SystemZ::WFADB:
1108+
case SystemZ::WFASB:
11131109
case SystemZ::WFAXB:
11141110
case SystemZ::VFADB:
11151111
case SystemZ::VFASB:
@@ -1129,21 +1125,21 @@ std::optional<unsigned>
11291125
SystemZInstrInfo::getInverseOpcode(unsigned Opcode) const {
11301126
// fadd => fsub
11311127
switch (Opcode) {
1132-
case SystemZ::WFADB_CCPseudo:
1133-
return SystemZ::WFSDB_CCPseudo;
1134-
case SystemZ::WFASB_CCPseudo:
1135-
return SystemZ::WFSSB_CCPseudo;
1128+
case SystemZ::WFADB:
1129+
return SystemZ::WFSDB;
1130+
case SystemZ::WFASB:
1131+
return SystemZ::WFSSB;
11361132
case SystemZ::WFAXB:
11371133
return SystemZ::WFSXB;
11381134
case SystemZ::VFADB:
11391135
return SystemZ::VFSDB;
11401136
case SystemZ::VFASB:
11411137
return SystemZ::VFSSB;
11421138
// fsub => fadd
1143-
case SystemZ::WFSDB_CCPseudo:
1144-
return SystemZ::WFADB_CCPseudo;
1145-
case SystemZ::WFSSB_CCPseudo:
1146-
return SystemZ::WFASB_CCPseudo;
1139+
case SystemZ::WFSDB:
1140+
return SystemZ::WFADB;
1141+
case SystemZ::WFSSB:
1142+
return SystemZ::WFASB;
11471143
case SystemZ::WFSXB:
11481144
return SystemZ::WFAXB;
11491145
case SystemZ::VFSDB:

‎llvm/lib/Target/SystemZ/SystemZInstrInfo.h

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -292,9 +292,6 @@ class SystemZInstrInfo : public SystemZGenInstrInfo {
292292
LiveIntervals *LIS) const override;
293293

294294
bool useMachineCombiner() const override { return true; }
295-
void
296-
finalizeInsInstrs(MachineInstr &Root, unsigned &P,
297-
SmallVectorImpl<MachineInstr *> &InsInstrs) const override;
298295
bool isAssociativeAndCommutative(const MachineInstr &Inst,
299296
bool Invert) const override;
300297
std::optional<unsigned> getInverseOpcode(unsigned Opcode) const override;

‎llvm/lib/Target/SystemZ/SystemZInstrVector.td

Lines changed: 16 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -1061,15 +1061,15 @@ multiclass VectorRounding<Instruction insn, TypedReg tr> {
10611061
let Predicates = [FeatureVector] in {
10621062
// Add.
10631063
let Uses = [FPC], mayRaiseFPException = 1, isCommutable = 1 in {
1064-
def VFA : BinaryVRRcFloatGeneric<"vfa", 0xE7E3>;
1065-
def VFADB : BinaryVRRc<"vfadb", 0xE7E3, any_fadd, v128db, v128db, 3, 0>;
1066-
defm WFADB : BinaryVRRcAndCCPseudo<"wfadb", 0xE7E3, any_fadd,
1067-
z_fadd_reassoc, v64db, v64db, 3, 8, 0, "adbr">;
1064+
def VFA : BinaryVRRcFloatGeneric<"vfa", 0xE7E3>;
1065+
def VFADB : BinaryVRRc<"vfadb", 0xE7E3, any_fadd, v128db, v128db, 3, 0>;
1066+
def WFADB : BinaryVRRc<"wfadb", 0xE7E3, any_fadd, v64db, v64db, 3, 8, 0,
1067+
"adbr">;
10681068
let Predicates = [FeatureVectorEnhancements1] in {
1069-
def VFASB : BinaryVRRc<"vfasb", 0xE7E3, any_fadd, v128sb, v128sb, 2, 0>;
1070-
defm WFASB : BinaryVRRcAndCCPseudo<"wfasb", 0xE7E3, any_fadd,
1071-
z_fadd_reassoc, v32sb, v32sb, 2, 8, 0, "aebr">;
1072-
def WFAXB : BinaryVRRc<"wfaxb", 0xE7E3, any_fadd, v128xb, v128xb, 4, 8>;
1069+
def VFASB : BinaryVRRc<"vfasb", 0xE7E3, any_fadd, v128sb, v128sb, 2, 0>;
1070+
def WFASB : BinaryVRRc<"wfasb", 0xE7E3, any_fadd, v32sb, v32sb, 2, 8, 0,
1071+
"aebr">;
1072+
def WFAXB : BinaryVRRc<"wfaxb", 0xE7E3, any_fadd, v128xb, v128xb, 4, 8>;
10731073
}
10741074
}
10751075

@@ -1389,15 +1389,15 @@ let Predicates = [FeatureVector] in {
13891389

13901390
// Subtract.
13911391
let Uses = [FPC], mayRaiseFPException = 1 in {
1392-
def VFS : BinaryVRRcFloatGeneric<"vfs", 0xE7E2>;
1393-
def VFSDB : BinaryVRRc<"vfsdb", 0xE7E2, any_fsub, v128db, v128db, 3, 0>;
1394-
defm WFSDB : BinaryVRRcAndCCPseudo<"wfsdb", 0xE7E2, any_fsub,
1395-
z_fsub_reassoc, v64db, v64db, 3, 8, 0, "sdbr">;
1392+
def VFS : BinaryVRRcFloatGeneric<"vfs", 0xE7E2>;
1393+
def VFSDB : BinaryVRRc<"vfsdb", 0xE7E2, any_fsub, v128db, v128db, 3, 0>;
1394+
def WFSDB : BinaryVRRc<"wfsdb", 0xE7E2, any_fsub, v64db, v64db, 3, 8, 0,
1395+
"sdbr">;
13961396
let Predicates = [FeatureVectorEnhancements1] in {
1397-
def VFSSB : BinaryVRRc<"vfssb", 0xE7E2, any_fsub, v128sb, v128sb, 2, 0>;
1398-
defm WFSSB : BinaryVRRcAndCCPseudo<"wfssb", 0xE7E2, any_fsub,
1399-
z_fsub_reassoc, v32sb, v32sb, 2, 8, 0, "sebr">;
1400-
def WFSXB : BinaryVRRc<"wfsxb", 0xE7E2, any_fsub, v128xb, v128xb, 4, 8>;
1397+
def VFSSB : BinaryVRRc<"vfssb", 0xE7E2, any_fsub, v128sb, v128sb, 2, 0>;
1398+
def WFSSB : BinaryVRRc<"wfssb", 0xE7E2, any_fsub, v32sb, v32sb, 2, 8, 0,
1399+
"sebr">;
1400+
def WFSXB : BinaryVRRc<"wfsxb", 0xE7E2, any_fsub, v128xb, v128xb, 4, 8>;
14011401
}
14021402
}
14031403

‎llvm/lib/Target/SystemZ/SystemZOperators.td

Lines changed: 0 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -841,15 +841,6 @@ def z_any_fmul_noreassoc : PatFrag<(ops node:$src1, node:$src2),
841841
(any_fmul node:$src1, node:$src2),
842842
[{ return !shouldSelectForReassoc(N); }]>;
843843

844-
// Floating-point operations which are reassociable, and therefore should be
845-
// selected as reg/reg instructions (no memop folding).
846-
def z_fadd_reassoc : PatFrag<(ops node:$src1, node:$src2),
847-
(fadd node:$src1, node:$src2),
848-
[{ return shouldSelectForReassoc(N); }]>;
849-
def z_fsub_reassoc : PatFrag<(ops node:$src1, node:$src2),
850-
(fsub node:$src1, node:$src2),
851-
[{ return shouldSelectForReassoc(N); }]>;
852-
853844
// Strict floating-point fragments.
854845
def z_any_fcmp : PatFrags<(ops node:$lhs, node:$rhs),
855846
[(z_strict_fcmp node:$lhs, node:$rhs),

‎llvm/lib/Target/SystemZ/SystemZScheduleZ13.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1344,7 +1344,7 @@ def : InstRW<[WLat3, WLat3, VecXsPm, NormalGr], (instregex "(V|W)FTCIDB$")>;
13441344
// Add / subtract
13451345
def : InstRW<[WLat8, VecBF2, NormalGr], (instregex "VF(A|S)$")>;
13461346
def : InstRW<[WLat8, VecBF2, NormalGr], (instregex "VF(A|S)DB$")>;
1347-
def : InstRW<[WLat7, VecBF, NormalGr], (instregex "WF(A|S)DB(_CCPseudo)?$")>;
1347+
def : InstRW<[WLat7, VecBF, NormalGr], (instregex "WF(A|S)DB$")>;
13481348

13491349
// Multiply / multiply-and-add/subtract
13501350
def : InstRW<[WLat8, VecBF2, NormalGr], (instregex "VFM$")>;

‎llvm/lib/Target/SystemZ/SystemZScheduleZ14.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1388,9 +1388,9 @@ def : InstRW<[WLat3, WLat3, VecDFX, NormalGr], (instregex "WFTCIXB$")>;
13881388
// Add / subtract
13891389
def : InstRW<[WLat8, VecBF2, NormalGr], (instregex "VF(A|S)$")>;
13901390
def : InstRW<[WLat7, VecBF, NormalGr], (instregex "VF(A|S)DB$")>;
1391-
def : InstRW<[WLat7, VecBF, NormalGr], (instregex "WF(A|S)DB(_CCPseudo)?$")>;
1391+
def : InstRW<[WLat7, VecBF, NormalGr], (instregex "WF(A|S)DB$")>;
13921392
def : InstRW<[WLat8, VecBF2, NormalGr], (instregex "VF(A|S)SB$")>;
1393-
def : InstRW<[WLat7, VecBF, NormalGr], (instregex "WF(A|S)SB(_CCPseudo)?$")>;
1393+
def : InstRW<[WLat7, VecBF, NormalGr], (instregex "WF(A|S)SB$")>;
13941394
def : InstRW<[WLat10, VecDF2, NormalGr], (instregex "WF(A|S)XB$")>;
13951395

13961396
// Multiply / multiply-and-add/subtract

‎llvm/lib/Target/SystemZ/SystemZScheduleZ15.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1431,9 +1431,9 @@ def : InstRW<[WLat3, WLat3, VecDFX, NormalGr], (instregex "WFTCIXB$")>;
14311431
// Add / subtract
14321432
def : InstRW<[WLat6, VecBF, NormalGr], (instregex "VF(A|S)$")>;
14331433
def : InstRW<[WLat6, VecBF, NormalGr], (instregex "VF(A|S)DB$")>;
1434-
def : InstRW<[WLat6, VecBF, NormalGr], (instregex "WF(A|S)DB(_CCPseudo)?$")>;
1434+
def : InstRW<[WLat6, VecBF, NormalGr], (instregex "WF(A|S)DB$")>;
14351435
def : InstRW<[WLat6, VecBF, NormalGr], (instregex "VF(A|S)SB$")>;
1436-
def : InstRW<[WLat6, VecBF, NormalGr], (instregex "WF(A|S)SB(_CCPseudo)?$")>;
1436+
def : InstRW<[WLat6, VecBF, NormalGr], (instregex "WF(A|S)SB$")>;
14371437
def : InstRW<[WLat10, VecDF2, NormalGr], (instregex "WF(A|S)XB$")>;
14381438

14391439
// Multiply / multiply-and-add/subtract

‎llvm/lib/Target/SystemZ/SystemZScheduleZ16.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1437,9 +1437,9 @@ def : InstRW<[WLat3, WLat3, VecDFX, NormalGr], (instregex "WFTCIXB$")>;
14371437
// Add / subtract
14381438
def : InstRW<[WLat6, VecBF, NormalGr], (instregex "VF(A|S)$")>;
14391439
def : InstRW<[WLat6, VecBF, NormalGr], (instregex "VF(A|S)DB$")>;
1440-
def : InstRW<[WLat6, VecBF, NormalGr], (instregex "WF(A|S)DB(_CCPseudo)?$")>;
1440+
def : InstRW<[WLat6, VecBF, NormalGr], (instregex "WF(A|S)DB$")>;
14411441
def : InstRW<[WLat6, VecBF, NormalGr], (instregex "VF(A|S)SB$")>;
1442-
def : InstRW<[WLat6, VecBF, NormalGr], (instregex "WF(A|S)SB(_CCPseudo)?$")>;
1442+
def : InstRW<[WLat6, VecBF, NormalGr], (instregex "WF(A|S)SB$")>;
14431443
def : InstRW<[WLat10, VecDF2, NormalGr], (instregex "WF(A|S)XB$")>;
14441444

14451445
// Multiply / multiply-and-add/subtract

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