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1 parent c07a1fe commit 148e55cCopy full SHA for 148e55c
llvm/docs/ReleaseNotes.rst
@@ -153,6 +153,7 @@ Changes to the RISC-V Backend
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"SiFive Custom Instruction Extension" as SiFive defines it. The LLVM project
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needs to work with SiFive to define and document real extension names for
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individual CSRs and instructions.
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+* ``-mcpu=sifive-p450`` was added.
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Changes to the WebAssembly Backend
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