s/spillable/foldable/

Author: nickdesaulniers

llvm/include/llvm/CodeGen/MachineInstr.h

@@ -1364,9 +1364,10 @@ class MachineInstr
     return getOpcode() == TargetOpcode::INLINEASM ||
            getOpcode() == TargetOpcode::INLINEASM_BR;
   }
-  /// Returns true if the memory operand can be folded. Does so by checking the
-  /// InlineAsm::Flag immediate operand at OpId - 1.
-  bool mayFoldInlineAsmMemOp(unsigned OpId) const;
+  /// Returns true if the register operand can be folded with a load or store
+  /// into a frame index. Does so by checking the InlineAsm::Flag immediate
+  /// operand at OpId - 1.
+  bool mayFoldInlineAsmRegOp(unsigned OpId) const;
 
   bool isStackAligningInlineAsm() const;
   InlineAsm::AsmDialect getInlineAsmDialect() const;

llvm/include/llvm/IR/InlineAsm.h

@@ -293,7 +293,7 @@ class InlineAsm final : public Value {
   //   Else:
   //     Bits 29-16 - The register class ID to use for the operand. (RegClass)
   //     Bit  30    - If the register is permitted to be spilled.
-  //                  (RegMayBeSpilled)
+  //                  (RegMayBeFolded)
   //                  Defaults to false "r", may be set for constraints like
   //                  "rm" (or "g").
   //
@@ -307,7 +307,7 @@ class InlineAsm final : public Value {
     using MatchedOperandNo = Bitfield::Element<unsigned, 16, 15>;
     using MemConstraintCode = Bitfield::Element<ConstraintCode, 16, 15, ConstraintCode::Max>;
     using RegClass = Bitfield::Element<unsigned, 16, 14>;
-    using RegMayBeSpilled = Bitfield::Element<bool, 30, 1>;
+    using RegMayBeFolded = Bitfield::Element<bool, 30, 1>;
     using IsMatched = Bitfield::Element<bool, 31, 1>;
 
 
@@ -428,15 +428,15 @@ class InlineAsm final : public Value {
     /// ("rm") vs ones it does not ("r"). This is because the inline asm may use
     /// instructions which don't support memory addressing modes for that
     /// operand.
-    void setRegMayBeSpilled(bool B) {
+    void setRegMayBeFolded(bool B) {
       assert((isRegDefKind() || isRegDefEarlyClobberKind() || isRegUseKind()) &&
              "Must be reg");
-      Bitfield::set<RegMayBeSpilled>(Storage, B);
+      Bitfield::set<RegMayBeFolded>(Storage, B);
     }
-    bool getRegMayBeSpilled() const {
+    bool getRegMayBeFolded() const {
       assert((isRegDefKind() || isRegDefEarlyClobberKind() || isRegUseKind()) &&
              "Must be reg");
-      return Bitfield::get<RegMayBeSpilled>(Storage);
+      return Bitfield::get<RegMayBeFolded>(Storage);
     }
   };
 

llvm/lib/CodeGen/MachineInstr.cpp

@@ -1794,8 +1794,8 @@ void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST,
 
       if ((F.isRegDefKind() || F.isRegDefEarlyClobberKind() ||
            F.isRegUseKind()) &&
-          F.getRegMayBeSpilled()) {
-        OS << " spillable";
+          F.getRegMayBeFolded()) {
+        OS << " foldable";
       }
 
       OS << ']';
@@ -2533,7 +2533,7 @@ void MachineInstr::insert(mop_iterator InsertBefore,
   }
 }
 
-bool MachineInstr::mayFoldInlineAsmMemOp(unsigned OpId) const {
+bool MachineInstr::mayFoldInlineAsmRegOp(unsigned OpId) const {
   assert(OpId && "expected non-zero operand id");
   assert(isInlineAsm() && "should only be used on inline asm");
 
@@ -2546,6 +2546,6 @@ bool MachineInstr::mayFoldInlineAsmMemOp(unsigned OpId) const {
 
   InlineAsm::Flag F(MD.getImm());
   if (F.isRegUseKind() || F.isRegDefKind() || F.isRegDefEarlyClobberKind())
-    return F.getRegMayBeSpilled();
+    return F.getRegMayBeFolded();
   return false;
 }

llvm/lib/CodeGen/TargetInstrInfo.cpp

@@ -1640,8 +1640,8 @@ std::string TargetInstrInfo::createMIROperandComment(
     OS << " tiedto:$" << TiedTo;
 
   if ((F.isRegDefKind() || F.isRegDefEarlyClobberKind() || F.isRegUseKind()) &&
-      F.getRegMayBeSpilled())
-    OS << " spillable";
+      F.getRegMayBeFolded())
+    OS << " foldable";
 
   return OS.str();
 }