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[RISCV] Match shl_vl (ext_vl v, splat 1) to vwadd_vl
Similer to: D153112, match shl (v, splat 1) to vwadd Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D154726
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‎llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td

Lines changed: 27 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1566,6 +1566,33 @@ defm : VPatBinaryWVL_VV_VX_WV_WX<riscv_vwaddu_vl, riscv_vwaddu_w_vl, "PseudoVWAD
15661566
defm : VPatBinaryWVL_VV_VX_WV_WX<riscv_vwsub_vl, riscv_vwsub_w_vl, "PseudoVWSUB">;
15671567
defm : VPatBinaryWVL_VV_VX_WV_WX<riscv_vwsubu_vl, riscv_vwsubu_w_vl, "PseudoVWSUBU">;
15681568

1569+
// shl_vl (ext_vl v, splat 1) is a special case of widening add.
1570+
foreach vtiToWti = AllWidenableIntVectors in {
1571+
defvar vti = vtiToWti.Vti;
1572+
defvar wti = vtiToWti.Wti;
1573+
let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,
1574+
GetVTypePredicates<wti>.Predicates) in {
1575+
def : Pat<(riscv_shl_vl (wti.Vector (riscv_sext_vl_oneuse
1576+
(vti.Vector vti.RegClass:$rs1),
1577+
(vti.Mask V0), VLOpFrag)),
1578+
(wti.Vector (riscv_vmv_v_x_vl
1579+
(wti.Vector undef), 1, VLOpFrag)),
1580+
wti.RegClass:$merge, (vti.Mask V0), VLOpFrag),
1581+
(!cast<Instruction>("PseudoVWADD_VV_"#vti.LMul.MX#"_MASK")
1582+
wti.RegClass:$merge, vti.RegClass:$rs1, vti.RegClass:$rs1,
1583+
(vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;
1584+
def : Pat<(riscv_shl_vl (wti.Vector (riscv_zext_vl_oneuse
1585+
(vti.Vector vti.RegClass:$rs1),
1586+
(vti.Mask V0), VLOpFrag)),
1587+
(wti.Vector (riscv_vmv_v_x_vl
1588+
(wti.Vector undef), 1, VLOpFrag)),
1589+
wti.RegClass:$merge, (vti.Mask V0), VLOpFrag),
1590+
(!cast<Instruction>("PseudoVWADDU_VV_"#vti.LMul.MX#"_MASK")
1591+
wti.RegClass:$merge, vti.RegClass:$rs1, vti.RegClass:$rs1,
1592+
(vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;
1593+
}
1594+
}
1595+
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// 11.3. Vector Integer Extension
15701597
defm : VPatExtendVL_V<riscv_zext_vl, "PseudoVZEXT", "VF2",
15711598
AllFractionableVF2IntVectors>;

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll

Lines changed: 4 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1863,10 +1863,8 @@ define <8 x i16> @mgather_baseidx_zext_v8i8_v8i16(ptr %base, <8 x i8> %idxs, <8
18631863
define <8 x i16> @mgather_baseidx_v8i16(ptr %base, <8 x i16> %idxs, <8 x i1> %m, <8 x i16> %passthru) {
18641864
; RV32-LABEL: mgather_baseidx_v8i16:
18651865
; RV32: # %bb.0:
1866-
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
1867-
; RV32-NEXT: vsext.vf2 v10, v8
1868-
; RV32-NEXT: vadd.vv v10, v10, v10
1869-
; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, mu
1866+
; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu
1867+
; RV32-NEXT: vwadd.vv v10, v8, v8
18701868
; RV32-NEXT: vluxei32.v v9, (a0), v10, v0.t
18711869
; RV32-NEXT: vmv.v.v v8, v9
18721870
; RV32-NEXT: ret
@@ -7802,10 +7800,8 @@ define <8 x half> @mgather_baseidx_zext_v8i8_v8f16(ptr %base, <8 x i8> %idxs, <8
78027800
define <8 x half> @mgather_baseidx_v8f16(ptr %base, <8 x i16> %idxs, <8 x i1> %m, <8 x half> %passthru) {
78037801
; RV32-LABEL: mgather_baseidx_v8f16:
78047802
; RV32: # %bb.0:
7805-
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
7806-
; RV32-NEXT: vsext.vf2 v10, v8
7807-
; RV32-NEXT: vadd.vv v10, v10, v10
7808-
; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, mu
7803+
; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu
7804+
; RV32-NEXT: vwadd.vv v10, v8, v8
78097805
; RV32-NEXT: vluxei32.v v9, (a0), v10, v0.t
78107806
; RV32-NEXT: vmv.v.v v8, v9
78117807
; RV32-NEXT: ret

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll

Lines changed: 4 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1444,10 +1444,8 @@ define void @mscatter_baseidx_zext_v8i8_v8i16(<8 x i16> %val, ptr %base, <8 x i8
14441444
define void @mscatter_baseidx_v8i16(<8 x i16> %val, ptr %base, <8 x i16> %idxs, <8 x i1> %m) {
14451445
; RV32-LABEL: mscatter_baseidx_v8i16:
14461446
; RV32: # %bb.0:
1447-
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
1448-
; RV32-NEXT: vsext.vf2 v10, v9
1449-
; RV32-NEXT: vadd.vv v10, v10, v10
1450-
; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, ma
1447+
; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma
1448+
; RV32-NEXT: vwadd.vv v10, v9, v9
14511449
; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t
14521450
; RV32-NEXT: ret
14531451
;
@@ -6699,10 +6697,8 @@ define void @mscatter_baseidx_zext_v8i8_v8f16(<8 x half> %val, ptr %base, <8 x i
66996697
define void @mscatter_baseidx_v8f16(<8 x half> %val, ptr %base, <8 x i16> %idxs, <8 x i1> %m) {
67006698
; RV32-LABEL: mscatter_baseidx_v8f16:
67016699
; RV32: # %bb.0:
6702-
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
6703-
; RV32-NEXT: vsext.vf2 v10, v9
6704-
; RV32-NEXT: vadd.vv v10, v10, v10
6705-
; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, ma
6700+
; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma
6701+
; RV32-NEXT: vwadd.vv v10, v9, v9
67066702
; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t
67076703
; RV32-NEXT: ret
67086704
;

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll

Lines changed: 4 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -555,9 +555,8 @@ define <8 x i16> @vpgather_baseidx_zext_v8i8_v8i16(ptr %base, <8 x i8> %idxs, <8
555555
define <8 x i16> @vpgather_baseidx_v8i16(ptr %base, <8 x i16> %idxs, <8 x i1> %m, i32 zeroext %evl) {
556556
; RV32-LABEL: vpgather_baseidx_v8i16:
557557
; RV32: # %bb.0:
558-
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
559-
; RV32-NEXT: vsext.vf2 v10, v8
560-
; RV32-NEXT: vadd.vv v10, v10, v10
558+
; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma
559+
; RV32-NEXT: vwadd.vv v10, v8, v8
561560
; RV32-NEXT: vsetvli zero, a1, e16, m1, ta, ma
562561
; RV32-NEXT: vluxei32.v v8, (a0), v10, v0.t
563562
; RV32-NEXT: ret
@@ -1319,9 +1318,8 @@ define <8 x half> @vpgather_baseidx_zext_v8i8_v8f16(ptr %base, <8 x i8> %idxs, <
13191318
define <8 x half> @vpgather_baseidx_v8f16(ptr %base, <8 x i16> %idxs, <8 x i1> %m, i32 zeroext %evl) {
13201319
; RV32-LABEL: vpgather_baseidx_v8f16:
13211320
; RV32: # %bb.0:
1322-
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
1323-
; RV32-NEXT: vsext.vf2 v10, v8
1324-
; RV32-NEXT: vadd.vv v10, v10, v10
1321+
; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma
1322+
; RV32-NEXT: vwadd.vv v10, v8, v8
13251323
; RV32-NEXT: vsetvli zero, a1, e16, m1, ta, ma
13261324
; RV32-NEXT: vluxei32.v v8, (a0), v10, v0.t
13271325
; RV32-NEXT: ret

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpscatter.ll

Lines changed: 4 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -400,9 +400,8 @@ define void @vpscatter_baseidx_zext_v8i8_v8i16(<8 x i16> %val, ptr %base, <8 x i
400400
define void @vpscatter_baseidx_v8i16(<8 x i16> %val, ptr %base, <8 x i16> %idxs, <8 x i1> %m, i32 zeroext %evl) {
401401
; RV32-LABEL: vpscatter_baseidx_v8i16:
402402
; RV32: # %bb.0:
403-
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
404-
; RV32-NEXT: vsext.vf2 v10, v9
405-
; RV32-NEXT: vadd.vv v10, v10, v10
403+
; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma
404+
; RV32-NEXT: vwadd.vv v10, v9, v9
406405
; RV32-NEXT: vsetvli zero, a1, e16, m1, ta, ma
407406
; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t
408407
; RV32-NEXT: ret
@@ -1127,9 +1126,8 @@ define void @vpscatter_baseidx_zext_v8i8_v8f16(<8 x half> %val, ptr %base, <8 x
11271126
define void @vpscatter_baseidx_v8f16(<8 x half> %val, ptr %base, <8 x i16> %idxs, <8 x i1> %m, i32 zeroext %evl) {
11281127
; RV32-LABEL: vpscatter_baseidx_v8f16:
11291128
; RV32: # %bb.0:
1130-
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
1131-
; RV32-NEXT: vsext.vf2 v10, v9
1132-
; RV32-NEXT: vadd.vv v10, v10, v10
1129+
; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma
1130+
; RV32-NEXT: vwadd.vv v10, v9, v9
11331131
; RV32-NEXT: vsetvli zero, a1, e16, m1, ta, ma
11341132
; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t
11351133
; RV32-NEXT: ret

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