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[AMDGPU][True16][CodeGen] gisel true16 for ICMP (#128913)
GlobalIsel true16 selection for ICMP
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+296
-61
lines changed

2 files changed

+296
-61
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llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

Lines changed: 16 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1478,10 +1478,21 @@ bool AMDGPUInstructionSelector::selectG_ICMP_or_FCMP(MachineInstr &I) const {
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if (Opcode == -1)
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return false;
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1481-
MachineInstr *ICmp = BuildMI(*BB, &I, DL, TII.get(Opcode),
1482-
I.getOperand(0).getReg())
1483-
.add(I.getOperand(2))
1484-
.add(I.getOperand(3));
1481+
MachineInstrBuilder ICmp;
1482+
// t16 instructions
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if (AMDGPU::hasNamedOperand(Opcode, AMDGPU::OpName::src0_modifiers)) {
1484+
ICmp = BuildMI(*BB, &I, DL, TII.get(Opcode), I.getOperand(0).getReg())
1485+
.addImm(0)
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.add(I.getOperand(2))
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.addImm(0)
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.add(I.getOperand(3))
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.addImm(0); // op_sel
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} else {
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ICmp = BuildMI(*BB, &I, DL, TII.get(Opcode), I.getOperand(0).getReg())
1492+
.add(I.getOperand(2))
1493+
.add(I.getOperand(3));
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}
1495+
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RBI.constrainGenericRegister(ICmp->getOperand(0).getReg(),
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*TRI.getBoolRC(), *MRI);
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bool Ret = constrainSelectedInstRegOperands(*ICmp, TII, TRI, RBI);
@@ -4596,6 +4607,7 @@ AMDGPUInstructionSelector::selectVOP3OpSelMods(MachineOperand &Root) const {
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}};
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}
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4610+
// FIXME-TRUE16 remove when fake16 is removed
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InstructionSelector::ComplexRendererFns
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AMDGPUInstructionSelector::selectVINTERPMods(MachineOperand &Root) const {
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Register Src;

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