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[AMDGPU] Fix crash due to assertion failure
Add check for FLAT instructions that dont use vector registers when computing VALU hazard. Change-Id: I558aed17b109047bdc64f8a7e5f419d4d37577cf
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3 files changed

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‎llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp

Lines changed: 6 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -858,9 +858,12 @@ int GCNHazardRecognizer::createsVALUHazard(const MachineInstr &MI) {
858858
}
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860860
if (TII->isFLAT(MI)) {
861-
int DataIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::vdata);
862-
if (AMDGPU::getRegBitWidth(Desc.operands()[DataIdx].RegClass) > 64)
863-
return DataIdx;
861+
// There is no hazard if the instruction does not use vector regs
862+
if (VDataIdx == -1)
863+
return -1;
864+
865+
if (AMDGPU::getRegBitWidth(VDataRCID) > 64)
866+
return VDataIdx;
864867
}
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return -1;

‎llvm/test/CodeGen/AMDGPU/fix-crash-valu-hazard.ll

Lines changed: 100 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,100 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -mtriple=amdgcn -mcpu=gfx942 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX942 %s
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; RUN: llc -mtriple=amdgcn -mcpu=gfx90a -O0 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX90A %s
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; RUN: llc -mtriple=amdgcn -mcpu=gfx90a -O0 -global-isel=true -verify-machineinstrs < %s | FileCheck -check-prefix=GFX90A-GISEL %s
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@G = global <2 x i32> splat (i32 5)
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define amdgpu_ps void @global_load_lds_dword_saddr(ptr addrspace(1) inreg nocapture %gptr, ptr addrspace(3) nocapture %lptr) {
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; GFX942-LABEL: global_load_lds_dword_saddr:
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; GFX942: ; %bb.0: ; %main_body
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; GFX942-NEXT: s_getpc_b64 s[2:3]
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; GFX942-NEXT: s_add_u32 s2, s2, G@gotpcrel32@lo+4
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; GFX942-NEXT: s_addc_u32 s3, s3, G@gotpcrel32@hi+12
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; GFX942-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
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; GFX942-NEXT: v_mov_b32_e32 v1, 0
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; GFX942-NEXT: s_waitcnt lgkmcnt(0)
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; GFX942-NEXT: v_mov_b64_e32 v[2:3], s[2:3]
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; GFX942-NEXT: flat_load_dwordx2 v[4:5], v[2:3]
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; GFX942-NEXT: v_readfirstlane_b32 s2, v0
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; GFX942-NEXT: s_mov_b32 m0, s2
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; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
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; GFX942-NEXT: v_mul_lo_u32 v0, v4, 10
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; GFX942-NEXT: global_load_lds_dword v1, s[0:1] offset:32 nt
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; GFX942-NEXT: v_mul_lo_u32 v1, v5, 10
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; GFX942-NEXT: s_waitcnt vmcnt(0)
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; GFX942-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
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; GFX942-NEXT: s_endpgm
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;
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; GFX90A-LABEL: global_load_lds_dword_saddr:
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; GFX90A: ; %bb.0: ; %main_body
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; GFX90A-NEXT: v_mov_b32_e32 v1, v0
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; GFX90A-NEXT: s_mov_b32 s2, s0
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; GFX90A-NEXT: ; kill: def $sgpr2 killed $sgpr2 def $sgpr2_sgpr3
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; GFX90A-NEXT: s_mov_b32 s3, s1
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; GFX90A-NEXT: ; kill: def $sgpr0_sgpr1 killed $sgpr2_sgpr3
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; GFX90A-NEXT: s_getpc_b64 s[0:1]
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; GFX90A-NEXT: s_add_u32 s0, s0, G@gotpcrel32@lo+4
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; GFX90A-NEXT: s_addc_u32 s1, s1, G@gotpcrel32@hi+12
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; GFX90A-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0
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; GFX90A-NEXT: s_waitcnt lgkmcnt(0)
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; GFX90A-NEXT: v_pk_mov_b32 v[2:3], s[0:1], s[0:1] op_sel:[0,1]
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; GFX90A-NEXT: flat_load_dwordx2 v[2:3], v[2:3]
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; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
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; GFX90A-NEXT: v_mov_b32_e32 v0, v3
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; GFX90A-NEXT: s_mov_b32 s4, 10
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; GFX90A-NEXT: v_mul_lo_u32 v0, v0, s4
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; GFX90A-NEXT: ; kill: def $vgpr2 killed $vgpr2 killed $vgpr2_vgpr3 killed $exec
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; GFX90A-NEXT: v_mul_lo_u32 v2, v2, s4
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; GFX90A-NEXT: ; implicit-def: $sgpr4
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; GFX90A-NEXT: ; implicit-def: $sgpr4
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; GFX90A-NEXT: ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec
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; GFX90A-NEXT: v_mov_b32_e32 v3, v0
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; GFX90A-NEXT: v_mov_b32_e32 v0, 0
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; GFX90A-NEXT: ; implicit-def: $sgpr4
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; GFX90A-NEXT: v_readfirstlane_b32 s4, v1
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; GFX90A-NEXT: s_mov_b32 m0, s4
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; GFX90A-NEXT: s_nop 0
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; GFX90A-NEXT: global_load_dword v0, s[2:3] offset:32 slc lds
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; GFX90A-NEXT: v_pk_mov_b32 v[0:1], s[0:1], s[0:1] op_sel:[0,1]
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; GFX90A-NEXT: s_waitcnt vmcnt(0)
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; GFX90A-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
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; GFX90A-NEXT: s_endpgm
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;
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; GFX90A-GISEL-LABEL: global_load_lds_dword_saddr:
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; GFX90A-GISEL: ; %bb.0: ; %main_body
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; GFX90A-GISEL-NEXT: s_mov_b32 s2, s0
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; GFX90A-GISEL-NEXT: ; kill: def $sgpr2 killed $sgpr2 def $sgpr2_sgpr3
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; GFX90A-GISEL-NEXT: s_mov_b32 s3, s1
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; GFX90A-GISEL-NEXT: s_mov_b32 s4, 10
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; GFX90A-GISEL-NEXT: s_getpc_b64 s[0:1]
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; GFX90A-GISEL-NEXT: s_add_u32 s0, s0, G@gotpcrel32@lo+4
72+
; GFX90A-GISEL-NEXT: s_addc_u32 s1, s1, G@gotpcrel32@hi+12
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; GFX90A-GISEL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0
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; GFX90A-GISEL-NEXT: s_waitcnt lgkmcnt(0)
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; GFX90A-GISEL-NEXT: v_pk_mov_b32 v[2:3], s[0:1], s[0:1] op_sel:[0,1]
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; GFX90A-GISEL-NEXT: flat_load_dwordx2 v[4:5], v[2:3]
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; GFX90A-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
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; GFX90A-GISEL-NEXT: v_mov_b32_e32 v2, v4
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; GFX90A-GISEL-NEXT: v_mov_b32_e32 v1, v5
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; GFX90A-GISEL-NEXT: v_mov_b32_e32 v3, s4
81+
; GFX90A-GISEL-NEXT: v_mul_lo_u32 v2, v2, v3
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; GFX90A-GISEL-NEXT: v_mov_b32_e32 v3, s4
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; GFX90A-GISEL-NEXT: v_mul_lo_u32 v1, v1, v3
84+
; GFX90A-GISEL-NEXT: ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec
85+
; GFX90A-GISEL-NEXT: v_mov_b32_e32 v3, v1
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; GFX90A-GISEL-NEXT: v_readfirstlane_b32 s4, v0
87+
; GFX90A-GISEL-NEXT: s_mov_b32 m0, s4
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; GFX90A-GISEL-NEXT: v_mov_b32_e32 v0, 0
89+
; GFX90A-GISEL-NEXT: global_load_dword v0, s[2:3] offset:32 slc lds
90+
; GFX90A-GISEL-NEXT: v_pk_mov_b32 v[0:1], s[0:1], s[0:1] op_sel:[0,1]
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; GFX90A-GISEL-NEXT: s_waitcnt vmcnt(0)
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; GFX90A-GISEL-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
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; GFX90A-GISEL-NEXT: s_endpgm
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main_body:
95+
%LGV = load <2 x i32>, ptr @G, align 8
96+
%B = mul <2 x i32> %LGV, splat (i32 10)
97+
call void @llvm.amdgcn.global.load.lds(ptr addrspace(1) %gptr, ptr addrspace(3) %lptr, i32 4, i32 32, i32 2)
98+
store <2 x i32> %B, ptr @G, align 8
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ret void
100+
}

‎llvm/test/CodeGen/AMDGPU/fix-crash-valu-hazard.mir

Lines changed: 54 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,54 @@
1+
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
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# RUN: llc -mtriple=amdgcn -mcpu=gfx942 -verify-machineinstrs -run-pass post-RA-hazard-rec -o - %s | FileCheck %s
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--- |
5+
@G = global <2 x i32> splat (i32 5)
6+
7+
define amdgpu_ps void @global_load_lds_dword_saddr(ptr addrspace(1) inreg nocapture %gptr, ptr addrspace(3) nocapture %lptr) #0 {
8+
main_body:
9+
%LGV = load <2 x i32>, ptr @G, align 8
10+
%B = mul <2 x i32> %LGV, splat (i32 10)
11+
call void @llvm.amdgcn.global.load.lds(ptr addrspace(1) %gptr, ptr addrspace(3) %lptr, i32 4, i32 32, i32 2)
12+
store <2 x i32> %B, ptr @G, align 8
13+
ret void
14+
}
15+
16+
attributes #0 = { "amdgpu-memory-bound"="true" "amdgpu-wave-limiter"="true" "target-cpu"="gfx942" }
17+
18+
...
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---
20+
name: global_load_lds_dword_saddr
21+
noVRegs: true
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body: |
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bb.0.main_body:
24+
liveins: $sgpr0, $sgpr1, $vgpr0
25+
26+
; CHECK-LABEL: name: global_load_lds_dword_saddr
27+
; CHECK: liveins: $sgpr0, $sgpr1, $vgpr0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: renamable $sgpr2_sgpr3 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-gotprel32-lo) @G, target-flags(amdgpu-gotprel32-hi) @G, implicit-def dead $scc
30+
; CHECK-NEXT: renamable $sgpr2_sgpr3 = S_LOAD_DWORDX2_IMM killed renamable $sgpr2_sgpr3, 0, 0 :: (dereferenceable invariant load (s64) from got, addrspace 4)
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; CHECK-NEXT: renamable $vgpr1 = V_MOV_B32_e32 0, implicit $exec
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; CHECK-NEXT: renamable $vgpr2_vgpr3 = COPY killed renamable $sgpr2_sgpr3
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; CHECK-NEXT: renamable $vgpr4_vgpr5 = FLAT_LOAD_DWORDX2 renamable $vgpr2_vgpr3, 0, 0, implicit $exec, implicit $flat_scr :: (dereferenceable load (s64) from @G)
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; CHECK-NEXT: renamable $sgpr2 = V_READFIRSTLANE_B32 killed $vgpr0, implicit $exec
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; CHECK-NEXT: $m0 = S_MOV_B32 killed renamable $sgpr2
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; CHECK-NEXT: S_NOP 0
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; CHECK-NEXT: GLOBAL_LOAD_LDS_DWORD_SADDR killed $sgpr0_sgpr1, killed $vgpr1, 32, 2, implicit $m0, implicit $exec :: (load (s32) from `ptr addrspace(1) poison` + 32, align 1, addrspace 1), (store (s32) into %ir.lptr + 32, addrspace 3)
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; CHECK-NEXT: renamable $vgpr1 = V_MUL_LO_U32_e64 $vgpr5, 10, implicit $exec
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; CHECK-NEXT: renamable $vgpr0 = V_MUL_LO_U32_e64 killed $vgpr4, 10, implicit $exec
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; CHECK-NEXT: FLAT_STORE_DWORDX2 killed renamable $vgpr2_vgpr3, killed renamable $vgpr0_vgpr1, 0, 0, implicit $exec, implicit $flat_scr :: (store (s64) into @G)
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; CHECK-NEXT: S_ENDPGM 0
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renamable $sgpr2_sgpr3 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-gotprel32-lo) @G, target-flags(amdgpu-gotprel32-hi) @G, implicit-def dead $scc
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renamable $sgpr2_sgpr3 = S_LOAD_DWORDX2_IMM killed renamable $sgpr2_sgpr3, 0, 0 :: (dereferenceable invariant load (s64) from got, addrspace 4)
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renamable $vgpr1 = V_MOV_B32_e32 0, implicit $exec
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renamable $vgpr2_vgpr3 = COPY killed renamable $sgpr2_sgpr3
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renamable $vgpr4_vgpr5 = FLAT_LOAD_DWORDX2 renamable $vgpr2_vgpr3, 0, 0, implicit $exec, implicit $flat_scr :: (dereferenceable load (s64) from @G)
47+
renamable $sgpr2 = V_READFIRSTLANE_B32 killed $vgpr0, implicit $exec
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$m0 = S_MOV_B32 killed renamable $sgpr2
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GLOBAL_LOAD_LDS_DWORD_SADDR killed $sgpr0_sgpr1, killed $vgpr1, 32, 2, implicit $m0, implicit $exec :: (load (s32) from `ptr addrspace(1) poison` + 32, align 1, addrspace 1), (store (s32) into %ir.lptr + 32, addrspace 3)
50+
renamable $vgpr1 = V_MUL_LO_U32_e64 $vgpr5, 10, implicit $exec
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renamable $vgpr0 = V_MUL_LO_U32_e64 killed $vgpr4, 10, implicit $exec
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FLAT_STORE_DWORDX2 killed renamable $vgpr2_vgpr3, killed renamable $vgpr0_vgpr1, 0, 0, implicit $exec, implicit $flat_scr :: (store (s64) into @G)
53+
S_ENDPGM 0
54+
...

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