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[X86] Add more tests for transform (icmp eq/ne (and X,C0),(shift X,C1)); PR71598
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‎llvm/test/CodeGen/X86/cmp-shiftX-maskX.ll

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@@ -570,6 +570,231 @@ define <16 x i1> @shl_to_ror_eq_16xi16_s8_fail_preserve_i16(<16 x i16> %x) {
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ret <16 x i1> %r
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}
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define i1 @shr_to_shl_eq_i32_s5_fail_doesnt_add_up(i32 %x) {
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; CHECK-LABEL: shr_to_shl_eq_i32_s5_fail_doesnt_add_up:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: andl $7, %eax
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; CHECK-NEXT: shrl $5, %edi
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; CHECK-NEXT: cmpl %edi, %eax
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; CHECK-NEXT: sete %al
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; CHECK-NEXT: retq
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%and = and i32 %x, 7
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%sh = lshr i32 %x, 5
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%r = icmp eq i32 %and, %sh
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ret i1 %r
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}
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define i1 @shr_to_shl_eq_i8_s5_fail_doesnt_add_up2(i32 %x) {
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; CHECK-LABEL: shr_to_shl_eq_i8_s5_fail_doesnt_add_up2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: andl $268435455, %eax # imm = 0xFFFFFFF
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; CHECK-NEXT: shrl $5, %edi
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; CHECK-NEXT: cmpl %edi, %eax
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; CHECK-NEXT: sete %al
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; CHECK-NEXT: retq
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%and = and i32 %x, 268435455
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%sh = lshr i32 %x, 5
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%r = icmp eq i32 %and, %sh
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ret i1 %r
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}
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define i1 @shr_to_shl_eq_i8_s5_fail_doesnt_add_up3(i32 %x) {
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; CHECK-LABEL: shr_to_shl_eq_i8_s5_fail_doesnt_add_up3:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: andl $67108863, %eax # imm = 0x3FFFFFF
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; CHECK-NEXT: shrl $5, %edi
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; CHECK-NEXT: cmpl %edi, %eax
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; CHECK-NEXT: sete %al
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; CHECK-NEXT: retq
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%and = and i32 %x, 67108863
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%sh = lshr i32 %x, 5
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%r = icmp eq i32 %and, %sh
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ret i1 %r
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}
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define i1 @shr_to_shl_eq_i8_s5_fail_doesnt_not_mask(i32 %x) {
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; CHECK-LABEL: shr_to_shl_eq_i8_s5_fail_doesnt_not_mask:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: andl $11, %eax
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; CHECK-NEXT: shrl $5, %edi
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; CHECK-NEXT: cmpl %edi, %eax
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; CHECK-NEXT: sete %al
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; CHECK-NEXT: retq
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%and = and i32 %x, 11
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%sh = lshr i32 %x, 5
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%r = icmp eq i32 %and, %sh
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ret i1 %r
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}
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define i1 @shl_to_shr_eq_i32_s9_fail_wrong_mask(i32 %x) {
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; CHECK-LABEL: shl_to_shr_eq_i32_s9_fail_wrong_mask:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: andl $511, %eax # imm = 0x1FF
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; CHECK-NEXT: shll $9, %edi
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; CHECK-NEXT: cmpl %edi, %eax
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; CHECK-NEXT: sete %al
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; CHECK-NEXT: retq
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%and = and i32 %x, 511
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%sh = shl i32 %x, 9
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%r = icmp eq i32 %and, %sh
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ret i1 %r
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}
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define i1 @shr_to_shl_eq_i32_s5_fail_wrong_mask(i32 %x) {
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; CHECK-LABEL: shr_to_shl_eq_i32_s5_fail_wrong_mask:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: andl $-32, %eax
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; CHECK-NEXT: shrl $5, %edi
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; CHECK-NEXT: cmpl %edi, %eax
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; CHECK-NEXT: sete %al
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; CHECK-NEXT: retq
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%and = and i32 %x, -32
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%sh = lshr i32 %x, 5
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%r = icmp eq i32 %and, %sh
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ret i1 %r
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}
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define i1 @shl_to_shr_eq_i32_s9_fail_doesnt_add_up(i32 %x) {
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; CHECK-LABEL: shl_to_shr_eq_i32_s9_fail_doesnt_add_up:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: andl $65024, %eax # imm = 0xFE00
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; CHECK-NEXT: shll $9, %edi
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; CHECK-NEXT: cmpl %edi, %eax
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; CHECK-NEXT: sete %al
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; CHECK-NEXT: retq
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%and = and i32 %x, 65024
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%sh = shl i32 %x, 9
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%r = icmp eq i32 %and, %sh
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ret i1 %r
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}
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define i1 @shl_to_shr_eq_i32_s9_fail_doesnt_add_up2(i32 %x) {
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; CHECK-LABEL: shl_to_shr_eq_i32_s9_fail_doesnt_add_up2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: andl $-1024, %eax # imm = 0xFC00
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; CHECK-NEXT: shll $9, %edi
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; CHECK-NEXT: cmpl %edi, %eax
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; CHECK-NEXT: sete %al
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; CHECK-NEXT: retq
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%and = and i32 %x, -1024
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%sh = shl i32 %x, 9
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%r = icmp eq i32 %and, %sh
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ret i1 %r
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}
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define i1 @shl_to_shr_eq_i32_s9_fail_doesnt_add_up3(i32 %x) {
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; CHECK-LABEL: shl_to_shr_eq_i32_s9_fail_doesnt_add_up3:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: andl $-256, %eax
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; CHECK-NEXT: shll $9, %edi
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; CHECK-NEXT: cmpl %edi, %eax
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; CHECK-NEXT: sete %al
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; CHECK-NEXT: retq
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%and = and i32 %x, -256
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%sh = shl i32 %x, 9
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%r = icmp eq i32 %and, %sh
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ret i1 %r
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}
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define i1 @shl_to_shr_eq_i32_s9_fail_not_mask(i32 %x) {
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; CHECK-LABEL: shl_to_shr_eq_i32_s9_fail_not_mask:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: andl $-511, %eax # imm = 0xFE01
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; CHECK-NEXT: shll $9, %edi
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; CHECK-NEXT: cmpl %edi, %eax
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; CHECK-NEXT: sete %al
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; CHECK-NEXT: retq
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%and = and i32 %x, -511
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%sh = shl i32 %x, 9
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%r = icmp eq i32 %and, %sh
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ret i1 %r
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}
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define i1 @shl_to_shr_eq_i32_s9_fail_not_mask2(i32 %x) {
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; CHECK-LABEL: shl_to_shr_eq_i32_s9_fail_not_mask2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: andl $-255, %eax
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; CHECK-NEXT: shll $9, %edi
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; CHECK-NEXT: cmpl %edi, %eax
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; CHECK-NEXT: sete %al
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; CHECK-NEXT: retq
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%and = and i32 %x, -255
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%sh = shl i32 %x, 9
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%r = icmp eq i32 %and, %sh
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ret i1 %r
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}
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define i1 @shl_to_shr_eq_i32_s9_fail_wrong_mask2(i32 %x) {
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; CHECK-LABEL: shl_to_shr_eq_i32_s9_fail_wrong_mask2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: andl $8388607, %eax # imm = 0x7FFFFF
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; CHECK-NEXT: shll $9, %edi
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; CHECK-NEXT: cmpl %edi, %eax
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; CHECK-NEXT: sete %al
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; CHECK-NEXT: retq
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%and = and i32 %x, 8388607
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%sh = shl i32 %x, 9
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%r = icmp eq i32 %and, %sh
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ret i1 %r
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}
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define i1 @shl_to_shr_eq_i32_s9(i32 %x) {
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; CHECK-LABEL: shl_to_shr_eq_i32_s9:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: andl $-512, %eax # imm = 0xFE00
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; CHECK-NEXT: shll $9, %edi
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; CHECK-NEXT: cmpl %edi, %eax
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; CHECK-NEXT: sete %al
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; CHECK-NEXT: retq
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%and = and i32 %x, -512
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%sh = shl i32 %x, 9
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%r = icmp eq i32 %and, %sh
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ret i1 %r
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}
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define i1 @shr_to_shl_eq_i32_s5(i32 %x) {
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; CHECK-LABEL: shr_to_shl_eq_i32_s5:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: andl $134217727, %eax # imm = 0x7FFFFFF
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; CHECK-NEXT: shrl $5, %edi
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; CHECK-NEXT: cmpl %edi, %eax
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; CHECK-NEXT: sete %al
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; CHECK-NEXT: retq
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%and = and i32 %x, 134217727
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%sh = lshr i32 %x, 5
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%r = icmp eq i32 %and, %sh
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ret i1 %r
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}
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define i1 @shr_to_rotate_eq_i32_s5(i32 %x) {
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; CHECK-LABEL: shr_to_rotate_eq_i32_s5:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: andl $268435455, %eax # imm = 0xFFFFFFF
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; CHECK-NEXT: shrl $4, %edi
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; CHECK-NEXT: cmpl %edi, %eax
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; CHECK-NEXT: sete %al
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; CHECK-NEXT: retq
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%and = and i32 %x, 268435455
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%sh = lshr i32 %x, 4
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%r = icmp eq i32 %and, %sh
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ret i1 %r
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}
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;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
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; CHECK-AVX: {{.*}}
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; CHECK-NOBMI-SSE2: {{.*}}

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