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[LLVM][CodeGen][SVE] Add ISel for bfloat scalable vector compares. (#138707)
1 parent 2a88feb commit 160abfb

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2 files changed

+1004
-3
lines changed

2 files changed

+1004
-3
lines changed

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1758,18 +1758,18 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
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for (auto Opcode :
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{ISD::FCEIL, ISD::FDIV, ISD::FFLOOR, ISD::FNEARBYINT, ISD::FRINT,
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ISD::FROUND, ISD::FROUNDEVEN, ISD::FSQRT, ISD::FTRUNC}) {
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ISD::FROUND, ISD::FROUNDEVEN, ISD::FSQRT, ISD::FTRUNC, ISD::SETCC}) {
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setOperationPromotedToType(Opcode, MVT::nxv2bf16, MVT::nxv2f32);
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setOperationPromotedToType(Opcode, MVT::nxv4bf16, MVT::nxv4f32);
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setOperationAction(Opcode, MVT::nxv8bf16, Expand);
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setOperationPromotedToType(Opcode, MVT::nxv8bf16, MVT::nxv8f32);
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}
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if (!Subtarget->hasSVEB16B16()) {
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for (auto Opcode : {ISD::FADD, ISD::FMA, ISD::FMAXIMUM, ISD::FMAXNUM,
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ISD::FMINIMUM, ISD::FMINNUM, ISD::FMUL, ISD::FSUB}) {
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setOperationPromotedToType(Opcode, MVT::nxv2bf16, MVT::nxv2f32);
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setOperationPromotedToType(Opcode, MVT::nxv4bf16, MVT::nxv4f32);
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setOperationAction(Opcode, MVT::nxv8bf16, Expand);
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setOperationPromotedToType(Opcode, MVT::nxv8bf16, MVT::nxv8f32);
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}
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}
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