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Commit 163e6a6

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shami
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Address review comments (2).
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llvm/lib/Target/X86/X86ISelLowering.cpp

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -31337,17 +31337,17 @@ static SDValue LowerBITREVERSE(SDValue Op, const X86Subtarget &Subtarget,
3133731337
if (VT.is256BitVector() && !Subtarget.hasInt256())
3133831338
return splitVectorIntUnary(Op, DAG, DL);
3133931339

31340-
// Lower i32/i64 to GFNI as i32/i64 -> Convert to vector (V = v16i32/v8i64) -> vXi8 BITREVERSE -> V[0] -> BSWAP
31341-
if (Subtarget.hasGFNI() && !VT.isVector()) {
31340+
// Lower i32/i64 to GFNI as vXi8 BITREVERSE + BSWAP
31341+
if (!VT.isVector()) {
3134231342

3134331343
assert ((VT.getScalarType() == MVT::i32) || (VT.getScalarType() == MVT::i64));
3134431344

31345-
auto ScalarType = VT.getScalarType();
31346-
auto CastTo = ScalarType == MVT::i32 ? MVT::v4i32 : MVT::v2i64;
31347-
SDValue Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, CastTo, In);
31345+
MVT SVT = VT.getScalarType();
31346+
MVT VecVT = MVT::getVectorVT(SVT, 128 / SVT.getSizeInBits());
31347+
SDValue Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, In);
3134831348
Res = DAG.getNode(ISD::BITREVERSE, DL, MVT::v16i8, DAG.getBitcast(MVT::v16i8, Res));
31349-
Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ScalarType, DAG.getBitcast(CastTo, Res), DAG.getIntPtrConstant(0, DL));
31350-
return DAG.getNode(ISD::BSWAP, DL, ScalarType, Res);
31349+
Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, SVT, DAG.getBitcast(VecVT, Res), DAG.getIntPtrConstant(0, DL));
31350+
return DAG.getNode(ISD::BSWAP, DL, SVT, Res);
3135131351
}
3135231352

3135331353
assert (VT.isVector() && VT.getSizeInBits() >= 128);

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