@@ -241,3 +241,84 @@ loop:
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exit:
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ret void
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}
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+
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+ declare i1 @cond ()
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+
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+ ; Test case for https://github.com/llvm/llvm-project/issues/131281.
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+ ; %add2 is known to not wrap via BTC.
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+ define void @no_signed_wrap_iv_via_btc (ptr %dst , i32 %N ) mustprogress {
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+ ; CHECK-LABEL: define void @no_signed_wrap_iv_via_btc
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+ ; CHECK-SAME: (ptr [[DST:%.*]], i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
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+ ; CHECK-NEXT: entry:
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+ ; CHECK-NEXT: [[SUB:%.*]] = add i32 [[N]], -100
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+ ; CHECK-NEXT: [[SUB4:%.*]] = add i32 [[N]], -99
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+ ; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[N]], 1
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+ ; CHECK-NEXT: [[SMAX:%.*]] = call i32 @llvm.smax.i32(i32 [[SUB4]], i32 [[TMP0]])
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+ ; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[SMAX]], 100
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+ ; CHECK-NEXT: [[TMP2:%.*]] = sub i32 [[TMP1]], [[N]]
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+ ; CHECK-NEXT: br label [[OUTER:%.*]]
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+ ; CHECK: outer.loopexit:
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+ ; CHECK-NEXT: br label [[OUTER]]
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+ ; CHECK: outer:
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+ ; CHECK-NEXT: [[C:%.*]] = call i1 @cond()
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+ ; CHECK-NEXT: br i1 [[C]], label [[LOOP_PREHEADER:%.*]], label [[EXIT:%.*]]
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+ ; CHECK: loop.preheader:
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+ ; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[TMP2]], 4
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+ ; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
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+ ; CHECK: vector.ph:
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+ ; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i32 [[TMP2]], 4
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+ ; CHECK-NEXT: [[N_VEC:%.*]] = sub i32 [[TMP2]], [[N_MOD_VF]]
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+ ; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
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+ ; CHECK: vector.body:
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+ ; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
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+ ; CHECK-NEXT: [[TMP3:%.*]] = add i32 [[INDEX]], 0
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+ ; CHECK-NEXT: [[TMP4:%.*]] = add i32 [[SUB4]], [[TMP3]]
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+ ; CHECK-NEXT: [[TMP5:%.*]] = sext i32 [[TMP4]] to i64
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+ ; CHECK-NEXT: [[TMP6:%.*]] = getelementptr i32, ptr [[DST]], i64 [[TMP5]]
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+ ; CHECK-NEXT: [[TMP7:%.*]] = getelementptr i32, ptr [[TMP6]], i32 0
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+ ; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr [[TMP7]], align 4
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+ ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4
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+ ; CHECK-NEXT: [[TMP8:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
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+ ; CHECK-NEXT: br i1 [[TMP8]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]]
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+ ; CHECK: middle.block:
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+ ; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[TMP2]], [[N_VEC]]
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+ ; CHECK-NEXT: br i1 [[CMP_N]], label [[OUTER_LOOPEXIT:%.*]], label [[SCALAR_PH]]
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+ ; CHECK: scalar.ph:
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+ ; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[LOOP_PREHEADER]] ]
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+ ; CHECK-NEXT: br label [[LOOP:%.*]]
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+ ; CHECK: loop:
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+ ; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[INC:%.*]], [[LOOP]] ], [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ]
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+ ; CHECK-NEXT: [[ADD2:%.*]] = add i32 [[SUB4]], [[IV]]
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+ ; CHECK-NEXT: [[ADD_EXT:%.*]] = sext i32 [[ADD2]] to i64
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+ ; CHECK-NEXT: [[GEP_DST:%.*]] = getelementptr i32, ptr [[DST]], i64 [[ADD_EXT]]
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+ ; CHECK-NEXT: store i32 0, ptr [[GEP_DST]], align 4
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+ ; CHECK-NEXT: [[INC]] = add i32 [[IV]], 1
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+ ; CHECK-NEXT: [[ADD:%.*]] = add i32 [[SUB]], [[INC]]
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+ ; CHECK-NEXT: [[EC:%.*]] = icmp sgt i32 [[ADD]], [[N]]
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+ ; CHECK-NEXT: br i1 [[EC]], label [[OUTER_LOOPEXIT]], label [[LOOP]], !llvm.loop [[LOOP9:![0-9]+]]
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+ ; CHECK: exit:
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+ ; CHECK-NEXT: ret void
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+ ;
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+ entry:
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+ %sub = add i32 %N , -100
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+ %sub4 = add i32 %N , -99
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+ br label %outer
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+
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+ outer:
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+ %c = call i1 @cond ()
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+ br i1 %c , label %loop , label %exit
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+
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+ loop:
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+ %iv = phi i32 [ 0 , %outer ], [ %inc , %loop ]
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+ %add2 = add i32 %sub4 , %iv
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+ %add.ext = sext i32 %add2 to i64
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+ %gep.dst = getelementptr i32 , ptr %dst , i64 %add.ext
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+ store i32 0 , ptr %gep.dst , align 4
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+ %inc = add i32 %iv , 1
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+ %add = add i32 %sub , %inc
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+ %ec = icmp sgt i32 %add , %N
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+ br i1 %ec , label %outer , label %loop
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+
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+ exit:
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+ ret void
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+ }
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