Skip to content

Commit 16994a6

Browse files
topperctopperc
authored
[RISCV] Add a PseudoVSETVLIX0X0 pseudo for the x0,x0 vsetvli. NFC (#141875)
Strengthen the register class on PseudoVSETVLIX0 to disallow X0 as a destination. This allows removal of an opcode check from RISCVDeadRegisterDefinitions. Now the register class will prevent the conversion to X0. I'm considering removing the explicit X0 operands and adding them during PseudoExpansion, but it complicates finding the vtype operand.
1 parent a926c61 commit 16994a6

File tree

8 files changed

+48
-52
lines changed

8 files changed

+48
-52
lines changed

‎llvm/lib/Target/RISCV/RISCVDeadRegisterDefinitions.cpp

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -74,9 +74,6 @@ bool RISCVDeadRegisterDefinitions::runOnMachineFunction(MachineFunction &MF) {
7474
MI.getOpcode() != RISCV::PseudoVSETVLI &&
7575
MI.getOpcode() != RISCV::PseudoVSETIVLI)
7676
continue;
77-
// For PseudoVSETVLIX0, Rd = X0 has special meaning.
78-
if (MI.getOpcode() == RISCV::PseudoVSETVLIX0)
79-
continue;
8077
for (int I = 0, E = Desc.getNumDefs(); I != E; ++I) {
8178
MachineOperand &MO = MI.getOperand(I);
8279
if (!MO.isReg() || !MO.isDef() || MO.isEarlyClobber())

‎llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp

Lines changed: 10 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -941,15 +941,13 @@ RISCVInsertVSETVLI::getInfoForVSETVLI(const MachineInstr &MI) const {
941941
} else {
942942
assert(MI.getOpcode() == RISCV::PseudoVSETVLI ||
943943
MI.getOpcode() == RISCV::PseudoVSETVLIX0);
944-
Register AVLReg = MI.getOperand(1).getReg();
945-
assert((AVLReg != RISCV::X0 || MI.getOperand(0).getReg() != RISCV::X0) &&
946-
"Can't handle X0, X0 vsetvli yet");
947-
if (AVLReg == RISCV::X0)
944+
if (MI.getOpcode() == RISCV::PseudoVSETVLIX0)
948945
NewInfo.setAVLVLMAX();
949946
else if (MI.getOperand(1).isUndef())
950947
// Otherwise use an AVL of 1 to avoid depending on previous vl.
951948
NewInfo.setAVLImm(1);
952949
else {
950+
Register AVLReg = MI.getOperand(1).getReg();
953951
VNInfo *VNI = getVNInfoFromReg(AVLReg, MI, LIS);
954952
NewInfo.setAVLRegDef(VNI, AVLReg);
955953
}
@@ -1056,7 +1054,7 @@ void RISCVInsertVSETVLI::insertVSETVLI(MachineBasicBlock &MBB,
10561054
// Use X0, X0 form if the AVL is the same and the SEW+LMUL gives the same
10571055
// VLMAX.
10581056
if (Info.hasSameAVL(PrevInfo) && Info.hasSameVLMAX(PrevInfo)) {
1059-
auto MI = BuildMI(MBB, InsertPt, DL, TII->get(RISCV::PseudoVSETVLIX0))
1057+
auto MI = BuildMI(MBB, InsertPt, DL, TII->get(RISCV::PseudoVSETVLIX0X0))
10601058
.addReg(RISCV::X0, RegState::Define | RegState::Dead)
10611059
.addReg(RISCV::X0, RegState::Kill)
10621060
.addImm(Info.encodeVTYPE())
@@ -1074,11 +1072,12 @@ void RISCVInsertVSETVLI::insertVSETVLI(MachineBasicBlock &MBB,
10741072
DefMI && RISCVInstrInfo::isVectorConfigInstr(*DefMI)) {
10751073
VSETVLIInfo DefInfo = getInfoForVSETVLI(*DefMI);
10761074
if (DefInfo.hasSameAVL(PrevInfo) && DefInfo.hasSameVLMAX(PrevInfo)) {
1077-
auto MI = BuildMI(MBB, InsertPt, DL, TII->get(RISCV::PseudoVSETVLIX0))
1078-
.addReg(RISCV::X0, RegState::Define | RegState::Dead)
1079-
.addReg(RISCV::X0, RegState::Kill)
1080-
.addImm(Info.encodeVTYPE())
1081-
.addReg(RISCV::VL, RegState::Implicit);
1075+
auto MI =
1076+
BuildMI(MBB, InsertPt, DL, TII->get(RISCV::PseudoVSETVLIX0X0))
1077+
.addReg(RISCV::X0, RegState::Define | RegState::Dead)
1078+
.addReg(RISCV::X0, RegState::Kill)
1079+
.addImm(Info.encodeVTYPE())
1080+
.addReg(RISCV::VL, RegState::Implicit);
10821081
if (LIS)
10831082
LIS->InsertMachineInstrInMaps(*MI);
10841083
return;
@@ -1098,7 +1097,7 @@ void RISCVInsertVSETVLI::insertVSETVLI(MachineBasicBlock &MBB,
10981097
}
10991098

11001099
if (Info.hasAVLVLMAX()) {
1101-
Register DestReg = MRI->createVirtualRegister(&RISCV::GPRRegClass);
1100+
Register DestReg = MRI->createVirtualRegister(&RISCV::GPRNoX0RegClass);
11021101
auto MI = BuildMI(MBB, InsertPt, DL, TII->get(RISCV::PseudoVSETVLIX0))
11031102
.addReg(DestReg, RegState::Define | RegState::Dead)
11041103
.addReg(RISCV::X0, RegState::Kill)

‎llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

Lines changed: 5 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -6056,7 +6056,7 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCodeGenOnly = 1 in {
60566056
PseudoInstExpansion<(CSRRS GPR:$rd, SysRegVLENB.Encoding, X0)>,
60576057
Sched<[WriteRdVLENB]>;
60586058
let Defs = [VL, VTYPE] in {
6059-
def PseudoReadVLENBViaVSETVLIX0 : Pseudo<(outs GPR:$rd), (ins uimm5:$shamt),
6059+
def PseudoReadVLENBViaVSETVLIX0 : Pseudo<(outs GPRNoX0:$rd), (ins uimm5:$shamt),
60606060
[]>,
60616061
Sched<[WriteVSETVLI, ReadVSETVLI]>;
60626062
}
@@ -6096,9 +6096,12 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0, Defs = [VL, VTYPE] in {
60966096
def PseudoVSETVLI : Pseudo<(outs GPR:$rd), (ins GPRNoX0:$rs1, VTypeIOp11:$vtypei), []>,
60976097
PseudoInstExpansion<(VSETVLI GPR:$rd, GPR:$rs1, VTypeIOp11:$vtypei)>,
60986098
Sched<[WriteVSETVLI, ReadVSETVLI]>;
6099-
def PseudoVSETVLIX0 : Pseudo<(outs GPR:$rd), (ins GPRX0:$rs1, VTypeIOp11:$vtypei), []>,
6099+
def PseudoVSETVLIX0 : Pseudo<(outs GPRNoX0:$rd), (ins GPRX0:$rs1, VTypeIOp11:$vtypei), []>,
61006100
PseudoInstExpansion<(VSETVLI GPR:$rd, GPR:$rs1, VTypeIOp11:$vtypei)>,
61016101
Sched<[WriteVSETVLI, ReadVSETVLI]>;
6102+
def PseudoVSETVLIX0X0 : Pseudo<(outs GPRX0:$rd), (ins GPRX0:$rs1, VTypeIOp11:$vtypei), []>,
6103+
PseudoInstExpansion<(VSETVLI GPR:$rd, GPR:$rs1, VTypeIOp11:$vtypei)>,
6104+
Sched<[WriteVSETVLI, ReadVSETVLI]>;
61026105
def PseudoVSETIVLI : Pseudo<(outs GPR:$rd), (ins uimm5:$rs1, VTypeIOp10:$vtypei), []>,
61036106
PseudoInstExpansion<(VSETIVLI GPR:$rd, uimm5:$rs1, VTypeIOp10:$vtypei)>,
61046107
Sched<[WriteVSETIVLI]>;

‎llvm/lib/Target/RISCV/RISCVInstrPredicates.td

Lines changed: 2 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -70,18 +70,15 @@ def isVectorConfigInstr
7070
CheckOpcode<[
7171
PseudoVSETVLI,
7272
PseudoVSETVLIX0,
73+
PseudoVSETVLIX0X0,
7374
PseudoVSETIVLI
7475
]>>>;
7576

7677
// Return true if this is 'vsetvli x0, x0, vtype' which preserves
7778
// VL and only sets VTYPE.
7879
def isVLPreservingConfig
7980
: TIIPredicate<"isVLPreservingConfig",
80-
MCReturnStatement<
81-
CheckAll<[
82-
CheckOpcode<[PseudoVSETVLIX0]>,
83-
CheckRegOperand<0, X0>
84-
]>>>;
81+
MCReturnStatement<CheckOpcode<[PseudoVSETVLIX0X0]>>>;
8582

8683
def isFloatScalarMoveOrScalarSplatInstr
8784
: TIIPredicate<"isFloatScalarMoveOrScalarSplatInstr",

‎llvm/test/CodeGen/RISCV/rvv/vmv-copy.mir

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -98,14 +98,14 @@ body: |
9898
; CHECK-NEXT: $v28m4 = PseudoVLE32_V_M4 undef $v28m4, killed $x16, $noreg, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
9999
; CHECK-NEXT: $x15 = PseudoVSETVLI $x17, 73 /* e16, m2, ta, mu */, implicit-def $vl, implicit-def $vtype
100100
; CHECK-NEXT: $v0m2 = PseudoVLE32_V_M2 undef $v0m2, $x18, $noreg, 4 /* e16 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
101-
; CHECK-NEXT: $x0 = PseudoVSETVLIX0 $x0, 82 /* e32, m4, ta, mu */, implicit-def $vl, implicit-def $vtype
101+
; CHECK-NEXT: $x0 = PseudoVSETVLIX0X0 $x0, 82 /* e32, m4, ta, mu */, implicit-def $vl, implicit-def $vtype
102102
; CHECK-NEXT: $v4m4 = PseudoVLE32_V_M4 undef $v4m4, killed $x18, $noreg, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
103103
; CHECK-NEXT: $v12m4 = VMV4R_V $v28m4, implicit $vtype
104104
$x15 = PseudoVSETVLI $x14, 82, implicit-def $vl, implicit-def $vtype
105105
$v28m4 = PseudoVLE32_V_M4 undef $v28m4, killed $x16, $noreg, 5, 0, implicit $vl, implicit $vtype
106106
$x15 = PseudoVSETVLI $x17, 73, implicit-def $vl, implicit-def $vtype
107107
$v0m2 = PseudoVLE32_V_M2 undef $v0m2, $x18, $noreg, 4, 0, implicit $vl, implicit $vtype
108-
$x0 = PseudoVSETVLIX0 $x0, 82, implicit-def $vl, implicit-def $vtype
108+
$x0 = PseudoVSETVLIX0X0 $x0, 82, implicit-def $vl, implicit-def $vtype
109109
$v4m4 = PseudoVLE32_V_M4 undef $v4m4, killed $x18, $noreg, 5, 0, implicit $vl, implicit $vtype
110110
$v12m4 = COPY $v28m4
111111
...
@@ -120,16 +120,16 @@ body: |
120120
; CHECK-NEXT: {{ $}}
121121
; CHECK-NEXT: $x15 = PseudoVSETVLI $x14, 82 /* e32, m4, ta, mu */, implicit-def $vl, implicit-def $vtype
122122
; CHECK-NEXT: $v28m4 = PseudoVLE32_V_M4 undef $v28m4, killed $x16, $noreg, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
123-
; CHECK-NEXT: $x0 = PseudoVSETVLIX0 $x0, 73 /* e16, m2, ta, mu */, implicit-def $vl, implicit-def $vtype
123+
; CHECK-NEXT: $x0 = PseudoVSETVLIX0X0 $x0, 73 /* e16, m2, ta, mu */, implicit-def $vl, implicit-def $vtype
124124
; CHECK-NEXT: $v0m2 = PseudoVLE32_V_M2 undef $v0m2, $x18, $noreg, 4 /* e16 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
125-
; CHECK-NEXT: $x0 = PseudoVSETVLIX0 $x0, 82 /* e32, m4, ta, mu */, implicit-def $vl, implicit-def $vtype
125+
; CHECK-NEXT: $x0 = PseudoVSETVLIX0X0 $x0, 82 /* e32, m4, ta, mu */, implicit-def $vl, implicit-def $vtype
126126
; CHECK-NEXT: $v4m4 = PseudoVLE32_V_M4 undef $v4m4, killed $x18, $noreg, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
127127
; CHECK-NEXT: $v12m4 = PseudoVMV_V_V_M4 undef $v12m4, $v28m4, $noreg, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
128128
$x15 = PseudoVSETVLI $x14, 82, implicit-def $vl, implicit-def $vtype
129129
$v28m4 = PseudoVLE32_V_M4 undef $v28m4, killed $x16, $noreg, 5, 0, implicit $vl, implicit $vtype
130-
$x0 = PseudoVSETVLIX0 $x0, 73, implicit-def $vl, implicit-def $vtype
130+
$x0 = PseudoVSETVLIX0X0 $x0, 73, implicit-def $vl, implicit-def $vtype
131131
$v0m2 = PseudoVLE32_V_M2 undef $v0m2, $x18, $noreg, 4, 0, implicit $vl, implicit $vtype
132-
$x0 = PseudoVSETVLIX0 $x0, 82, implicit-def $vl, implicit-def $vtype
132+
$x0 = PseudoVSETVLIX0X0 $x0, 82, implicit-def $vl, implicit-def $vtype
133133
$v4m4 = PseudoVLE32_V_M4 undef $v4m4, killed $x18, $noreg, 5, 0, implicit $vl, implicit $vtype
134134
$v12m4 = COPY $v28m4
135135
...
@@ -144,12 +144,12 @@ body: |
144144
; CHECK-NEXT: {{ $}}
145145
; CHECK-NEXT: $x15 = PseudoVSETVLI $x14, 82 /* e32, m4, ta, mu */, implicit-def $vl, implicit-def $vtype
146146
; CHECK-NEXT: $v28m4 = PseudoVLE32_V_M4 undef $v28m4, killed $x16, $noreg, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
147-
; CHECK-NEXT: $x0 = PseudoVSETVLIX0 $x0, 73 /* e16, m2, ta, mu */, implicit-def $vl, implicit-def $vtype
147+
; CHECK-NEXT: $x0 = PseudoVSETVLIX0X0 $x0, 73 /* e16, m2, ta, mu */, implicit-def $vl, implicit-def $vtype
148148
; CHECK-NEXT: $v0m2 = PseudoVLE32_V_M2 undef $v0m2, $x18, $noreg, 4 /* e16 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
149149
; CHECK-NEXT: $v12m4 = VMV4R_V $v28m4, implicit $vtype
150150
$x15 = PseudoVSETVLI $x14, 82, implicit-def $vl, implicit-def $vtype
151151
$v28m4 = PseudoVLE32_V_M4 undef $v28m4, killed $x16, $noreg, 5, 0, implicit $vl, implicit $vtype
152-
$x0 = PseudoVSETVLIX0 $x0, 73, implicit-def $vl, implicit-def $vtype
152+
$x0 = PseudoVSETVLIX0X0 $x0, 73, implicit-def $vl, implicit-def $vtype
153153
$v0m2 = PseudoVLE32_V_M2 undef $v0m2, $x18, $noreg, 4, 0, implicit $vl, implicit $vtype
154154
$v12m4 = COPY $v28m4
155155
...
@@ -185,11 +185,11 @@ body: |
185185
; CHECK-NEXT: {{ $}}
186186
; CHECK-NEXT: $x15 = PseudoVSETVLI $x14, 82 /* e32, m4, ta, mu */, implicit-def $vl, implicit-def $vtype
187187
; CHECK-NEXT: $v28m4 = PseudoVLE32_V_M4 undef $v28m4, killed $x16, $noreg, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
188-
; CHECK-NEXT: $x0 = PseudoVSETVLIX0 $x0, 74 /* e16, m4, ta, mu */, implicit-def $vl, implicit-def $vtype
188+
; CHECK-NEXT: $x0 = PseudoVSETVLIX0X0 $x0, 74 /* e16, m4, ta, mu */, implicit-def $vl, implicit-def $vtype
189189
; CHECK-NEXT: $v12m4 = VMV4R_V $v28m4, implicit $vtype
190190
$x15 = PseudoVSETVLI $x14, 82, implicit-def $vl, implicit-def $vtype
191191
$v28m4 = PseudoVLE32_V_M4 undef $v28m4, killed $x16, $noreg, 5, 0, implicit $vl, implicit $vtype
192-
$x0 = PseudoVSETVLIX0 $x0, 74, implicit-def $vl, implicit-def $vtype
192+
$x0 = PseudoVSETVLIX0X0 $x0, 74, implicit-def $vl, implicit-def $vtype
193193
$v12m4 = COPY $v28m4
194194
...
195195
---

‎llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-coalesce.mir

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -15,7 +15,7 @@ body: |
1515
; CHECK-NEXT: bb.1:
1616
; CHECK-NEXT: successors: %bb.2(0x80000000)
1717
; CHECK-NEXT: {{ $}}
18-
; CHECK-NEXT: dead [[PseudoVSETVLIX0_:%[0-9]+]]:gpr = PseudoVSETVLIX0 killed $x0, 209 /* e32, m2, ta, ma */, implicit-def $vl, implicit-def $vtype
18+
; CHECK-NEXT: dead [[PseudoVSETVLIX0_:%[0-9]+]]:gprnox0 = PseudoVSETVLIX0 killed $x0, 209 /* e32, m2, ta, ma */, implicit-def $vl, implicit-def $vtype
1919
; CHECK-NEXT: renamable $v10m2 = PseudoVMV_V_I_M2 undef renamable $v10m2, 0, -1, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
2020
; CHECK-NEXT: {{ $}}
2121
; CHECK-NEXT: bb.2:

0 commit comments

Comments
 (0)