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Commit 16c1791

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add m68k isel support for non-ARI atomic loads/stores
1 parent e504c85 commit 16c1791

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2 files changed

+22
-2
lines changed

2 files changed

+22
-2
lines changed

llvm/lib/Target/M68k/M68kISelDAGToDAG.cpp

Lines changed: 15 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -772,6 +772,20 @@ static bool isAddressBase(const SDValue &N) {
772772
}
773773
}
774774

775+
static bool AllowARIIWithZeroDisp(SDNode *Parent) {
776+
if (!Parent)
777+
return false;
778+
switch (Parent->getOpcode()) {
779+
case ISD::LOAD:
780+
case ISD::STORE:
781+
case ISD::ATOMIC_LOAD:
782+
case ISD::ATOMIC_STORE:
783+
return true;
784+
default:
785+
return false;
786+
}
787+
}
788+
775789
bool M68kDAGToDAGISel::SelectARII(SDNode *Parent, SDValue N, SDValue &Disp,
776790
SDValue &Base, SDValue &Index) {
777791
M68kISelAddressMode AM(M68kISelAddressMode::AddrType::ARII);
@@ -811,8 +825,7 @@ bool M68kDAGToDAGISel::SelectARII(SDNode *Parent, SDValue N, SDValue &Disp,
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// The idea here is that we want to use AddrType::ARII without displacement
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// only if necessary like memory operations, otherwise this must be lowered
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// into addition
814-
if (AM.Disp == 0 && (!Parent || (Parent->getOpcode() != ISD::LOAD &&
815-
Parent->getOpcode() != ISD::STORE))) {
828+
if (AM.Disp == 0 && !AllowARIIWithZeroDisp(Parent)) {
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LLVM_DEBUG(dbgs() << "REJECT: Displacement is Zero\n");
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return false;
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}

llvm/lib/Target/M68k/M68kInstrAtomics.td

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -10,9 +10,16 @@ foreach size = [8, 16, 32] in {
1010
def : Pat<(!cast<SDPatternOperator>("atomic_load_"#size) MxCP_ARI:$ptr),
1111
(!cast<MxInst>("MOV"#size#"dj") !cast<MxMemOp>("MxARI"#size):$ptr)>;
1212

13+
def : Pat<(!cast<SDPatternOperator>("atomic_load_"#size) MxCP_ARII:$ptr),
14+
(!cast<MxInst>("MOV"#size#"df") !cast<MxMemOp>("MxARII"#size):$ptr)>;
15+
1316
def : Pat<(!cast<SDPatternOperator>("atomic_store_"#size) !cast<MxRegOp>("MxDRD"#size):$val, MxCP_ARI:$ptr),
1417
(!cast<MxInst>("MOV"#size#"jd") !cast<MxMemOp>("MxARI"#size):$ptr,
1518
!cast<MxRegOp>("MxDRD"#size):$val)>;
19+
20+
def : Pat<(!cast<SDPatternOperator>("atomic_store_"#size) !cast<MxRegOp>("MxDRD"#size):$val, MxCP_ARII:$ptr),
21+
(!cast<MxInst>("MOV"#size#"fd") !cast<MxMemOp>("MxARII"#size):$ptr,
22+
!cast<MxRegOp>("MxDRD"#size):$val)>;
1623
}
1724

1825
let Predicates = [AtLeastM68020] in {

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