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[NFC][DirectX] Enforce ordering of DXIL Ops in DXIL.td
- this reorders existing dxil ops to be in ascending order with respect to their opcodes - this helps be consistent with dxil.rst and other resources listing the opcodes
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‎llvm/lib/Target/DirectX/DXIL.td

Lines changed: 99 additions & 97 deletions
Original file line numberDiff line numberDiff line change
@@ -405,6 +405,8 @@ class DXILOp<int opcode, DXILOpClass opclass> {
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}
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// Concrete definitions of DXIL Operations
408+
//
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// This are sorted by ascending value of the DXIL Opcodes
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409411
def Abs : DXILOp<6, unary> {
410412
let Doc = "Returns the absolute value of the input.";
@@ -855,6 +857,20 @@ def CheckAccessFullyMapped : DXILOp<71, checkAccessFullyMapped> {
855857
let attributes = [Attributes<DXIL1_0, [ReadOnly]>];
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}
857859

860+
def Barrier : DXILOp<80, barrier> {
861+
let Doc = "inserts a memory barrier in the shader";
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let intrinsics = [
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IntrinSelect<int_dx_group_memory_barrier_with_group_sync,
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[IntrinArgI32<BarrierMode_GroupMemoryBarrierWithGroupSync>]>,
865+
];
866+
867+
let arguments = [Int32Ty];
868+
let result = VoidTy;
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let stages = [Stages<DXIL1_0, [compute, library]>];
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let attributes = [Attributes<DXIL1_0, []>];
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let properties = [IsBarrier];
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}
873+
858874
def Discard : DXILOp<82, discard> {
859875
let Doc = "discard the current pixel";
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let intrinsics = [IntrinSelect<int_dx_discard>];
@@ -921,6 +937,89 @@ def SplitDouble : DXILOp<102, splitDouble> {
921937
let attributes = [Attributes<DXIL1_0, [ReadNone]>];
922938
}
923939

940+
def WaveIsFirstLane : DXILOp<110, waveIsFirstLane> {
941+
let Doc = "returns 1 for the first lane in the wave";
942+
let intrinsics = [IntrinSelect<int_dx_wave_is_first_lane>];
943+
let arguments = [];
944+
let result = Int1Ty;
945+
let stages = [Stages<DXIL1_0, [all_stages]>];
946+
let properties = [IsWave];
947+
}
948+
949+
def WaveGetLaneIndex : DXILOp<111, waveGetLaneIndex> {
950+
let Doc = "returns the index of the current lane in the wave";
951+
let intrinsics = [IntrinSelect<int_dx_wave_getlaneindex>];
952+
let arguments = [];
953+
let result = Int32Ty;
954+
let stages = [Stages<DXIL1_0, [all_stages]>];
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let attributes = [Attributes<DXIL1_0, [ReadOnly]>];
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let properties = [IsWave];
957+
}
958+
959+
def WaveActiveAnyTrue : DXILOp<113, waveAnyTrue> {
960+
let Doc = "returns true if the expression is true in any of the active lanes "
961+
"in the current wave";
962+
let intrinsics = [IntrinSelect<int_dx_wave_any>];
963+
let arguments = [Int1Ty];
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let result = Int1Ty;
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let stages = [Stages<DXIL1_0, [all_stages]>];
966+
let properties = [IsWave];
967+
}
968+
969+
def WaveActiveAllTrue : DXILOp<114, waveAllTrue> {
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let Doc = "returns true if the expression is true in all of the active lanes "
971+
"in the current wave";
972+
let intrinsics = [IntrinSelect<int_dx_wave_all>];
973+
let arguments = [Int1Ty];
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let result = Int1Ty;
975+
let stages = [Stages<DXIL1_0, [all_stages]>];
976+
let properties = [IsWave];
977+
}
978+
979+
def WaveReadLaneAt : DXILOp<117, waveReadLaneAt> {
980+
let Doc = "returns the value from the specified lane";
981+
let intrinsics = [IntrinSelect<int_dx_wave_readlane>];
982+
let arguments = [OverloadTy, Int32Ty];
983+
let result = OverloadTy;
984+
let overloads = [Overloads<
985+
DXIL1_0, [HalfTy, FloatTy, DoubleTy, Int1Ty, Int16Ty, Int32Ty, Int64Ty]>];
986+
let stages = [Stages<DXIL1_0, [all_stages]>];
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let properties = [IsWave];
988+
}
989+
990+
def WaveActiveOp : DXILOp<119, waveActiveOp> {
991+
let Doc = "returns the result of the operation across waves";
992+
let intrinsics = [
993+
IntrinSelect<int_dx_wave_reduce_sum,
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[
995+
IntrinArgIndex<0>, IntrinArgI8<WaveOpKind_Sum>,
996+
IntrinArgI8<SignedOpKind_Signed>
997+
]>,
998+
IntrinSelect<int_dx_wave_reduce_usum,
999+
[
1000+
IntrinArgIndex<0>, IntrinArgI8<WaveOpKind_Sum>,
1001+
IntrinArgI8<SignedOpKind_Unsigned>
1002+
]>,
1003+
];
1004+
1005+
let arguments = [OverloadTy, Int8Ty, Int8Ty];
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let result = OverloadTy;
1007+
let overloads = [
1008+
Overloads<DXIL1_0, [HalfTy, FloatTy, DoubleTy, Int16Ty, Int32Ty, Int64Ty]>
1009+
];
1010+
let stages = [Stages<DXIL1_0, [all_stages]>];
1011+
let attributes = [Attributes<DXIL1_0, [ReadNone]>];
1012+
}
1013+
1014+
def WaveAllBitCount : DXILOp<135, waveAllOp> {
1015+
let Doc = "returns the count of bits set to 1 across the wave";
1016+
let intrinsics = [IntrinSelect<int_dx_wave_active_countbits>];
1017+
let arguments = [Int1Ty];
1018+
let result = Int32Ty;
1019+
let stages = [Stages<DXIL1_0, [all_stages]>];
1020+
let properties = [IsWave];
1021+
}
1022+
9241023
def RawBufferLoad : DXILOp<139, rawBufferLoad> {
9251024
let Doc = "reads from a raw buffer and structured buffer";
9261025
// Handle, Coord0, Coord1, Mask, Alignment
@@ -993,100 +1092,3 @@ def CreateHandleFromBinding : DXILOp<217, createHandleFromBinding> {
9931092
let stages = [Stages<DXIL1_6, [all_stages]>];
9941093
let attributes = [Attributes<DXIL1_0, [ReadNone]>];
9951094
}
996-
997-
def WaveActiveAllTrue : DXILOp<114, waveAllTrue> {
998-
let Doc = "returns true if the expression is true in all of the active lanes "
999-
"in the current wave";
1000-
let intrinsics = [IntrinSelect<int_dx_wave_all>];
1001-
let arguments = [Int1Ty];
1002-
let result = Int1Ty;
1003-
let stages = [Stages<DXIL1_0, [all_stages]>];
1004-
let properties = [IsWave];
1005-
}
1006-
1007-
def WaveActiveAnyTrue : DXILOp<113, waveAnyTrue> {
1008-
let Doc = "returns true if the expression is true in any of the active lanes "
1009-
"in the current wave";
1010-
let intrinsics = [IntrinSelect<int_dx_wave_any>];
1011-
let arguments = [Int1Ty];
1012-
let result = Int1Ty;
1013-
let stages = [Stages<DXIL1_0, [all_stages]>];
1014-
let properties = [IsWave];
1015-
}
1016-
1017-
def WaveActiveOp : DXILOp<119, waveActiveOp> {
1018-
let Doc = "returns the result of the operation across waves";
1019-
let intrinsics = [
1020-
IntrinSelect<int_dx_wave_reduce_sum,
1021-
[
1022-
IntrinArgIndex<0>, IntrinArgI8<WaveOpKind_Sum>,
1023-
IntrinArgI8<SignedOpKind_Signed>
1024-
]>,
1025-
IntrinSelect<int_dx_wave_reduce_usum,
1026-
[
1027-
IntrinArgIndex<0>, IntrinArgI8<WaveOpKind_Sum>,
1028-
IntrinArgI8<SignedOpKind_Unsigned>
1029-
]>,
1030-
];
1031-
1032-
let arguments = [OverloadTy, Int8Ty, Int8Ty];
1033-
let result = OverloadTy;
1034-
let overloads = [
1035-
Overloads<DXIL1_0, [HalfTy, FloatTy, DoubleTy, Int16Ty, Int32Ty, Int64Ty]>
1036-
];
1037-
let stages = [Stages<DXIL1_0, [all_stages]>];
1038-
let attributes = [Attributes<DXIL1_0, [ReadNone]>];
1039-
}
1040-
1041-
def WaveIsFirstLane : DXILOp<110, waveIsFirstLane> {
1042-
let Doc = "returns 1 for the first lane in the wave";
1043-
let intrinsics = [IntrinSelect<int_dx_wave_is_first_lane>];
1044-
let arguments = [];
1045-
let result = Int1Ty;
1046-
let stages = [Stages<DXIL1_0, [all_stages]>];
1047-
let properties = [IsWave];
1048-
}
1049-
1050-
def WaveReadLaneAt : DXILOp<117, waveReadLaneAt> {
1051-
let Doc = "returns the value from the specified lane";
1052-
let intrinsics = [IntrinSelect<int_dx_wave_readlane>];
1053-
let arguments = [OverloadTy, Int32Ty];
1054-
let result = OverloadTy;
1055-
let overloads = [Overloads<
1056-
DXIL1_0, [HalfTy, FloatTy, DoubleTy, Int1Ty, Int16Ty, Int32Ty, Int64Ty]>];
1057-
let stages = [Stages<DXIL1_0, [all_stages]>];
1058-
let properties = [IsWave];
1059-
}
1060-
1061-
def WaveGetLaneIndex : DXILOp<111, waveGetLaneIndex> {
1062-
let Doc = "returns the index of the current lane in the wave";
1063-
let intrinsics = [IntrinSelect<int_dx_wave_getlaneindex>];
1064-
let arguments = [];
1065-
let result = Int32Ty;
1066-
let stages = [Stages<DXIL1_0, [all_stages]>];
1067-
let attributes = [Attributes<DXIL1_0, [ReadOnly]>];
1068-
let properties = [IsWave];
1069-
}
1070-
1071-
def WaveAllBitCount : DXILOp<135, waveAllOp> {
1072-
let Doc = "returns the count of bits set to 1 across the wave";
1073-
let intrinsics = [IntrinSelect<int_dx_wave_active_countbits>];
1074-
let arguments = [Int1Ty];
1075-
let result = Int32Ty;
1076-
let stages = [Stages<DXIL1_0, [all_stages]>];
1077-
let properties = [IsWave];
1078-
}
1079-
1080-
def Barrier : DXILOp<80, barrier> {
1081-
let Doc = "inserts a memory barrier in the shader";
1082-
let intrinsics = [
1083-
IntrinSelect<int_dx_group_memory_barrier_with_group_sync,
1084-
[IntrinArgI32<BarrierMode_GroupMemoryBarrierWithGroupSync>]>,
1085-
];
1086-
1087-
let arguments = [Int32Ty];
1088-
let result = VoidTy;
1089-
let stages = [Stages<DXIL1_0, [compute, library]>];
1090-
let attributes = [Attributes<DXIL1_0, []>];
1091-
let properties = [IsBarrier];
1092-
}

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