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Merge setDefMI into setReg
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llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp

Lines changed: 15 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -463,7 +463,7 @@ class VSETVLIInfo {
463463

464464
enum : uint8_t {
465465
Uninitialized,
466-
AVLIsReg,
466+
AVLIsDefMI,
467467
AVLIsImm,
468468
AVLIsVLMAX,
469469
AVLIsIgnored,
@@ -492,10 +492,11 @@ class VSETVLIInfo {
492492
void setUnknown() { State = Unknown; }
493493
bool isUnknown() const { return State == Unknown; }
494494

495-
void setAVLReg(Register Reg) {
495+
void setAVLReg(Register Reg, const MachineInstr *DefMI) {
496496
assert(Reg.isVirtual());
497497
AVLReg = Reg;
498-
State = AVLIsReg;
498+
AVLDefMI = DefMI;
499+
State = AVLIsDefMI;
499500
}
500501

501502
void setAVLImm(unsigned Imm) {
@@ -509,7 +510,7 @@ class VSETVLIInfo {
509510
void setAVLDefMI(const MachineInstr *DefMI) { AVLDefMI = DefMI; }
510511

511512
bool hasAVLImm() const { return State == AVLIsImm; }
512-
bool hasAVLReg() const { return State == AVLIsReg; }
513+
bool hasAVLReg() const { return State == AVLIsDefMI; }
513514
bool hasAVLVLMAX() const { return State == AVLIsVLMAX; }
514515
bool hasAVLIgnored() const { return State == AVLIsIgnored; }
515516
Register getAVLReg() const {
@@ -527,10 +528,8 @@ class VSETVLIInfo {
527528
assert(Info.isValid());
528529
if (Info.isUnknown())
529530
setUnknown();
530-
else if (Info.hasAVLReg()) {
531-
setAVLReg(Info.getAVLReg());
532-
setAVLDefMI(Info.getAVLDefMI());
533-
}
531+
else if (Info.hasAVLReg())
532+
setAVLReg(Info.getAVLReg(), Info.getAVLDefMI());
534533
else if (Info.hasAVLVLMAX())
535534
setAVLVLMAX();
536535
else if (Info.hasAVLIgnored())
@@ -890,7 +889,7 @@ static VSETVLIInfo getInfoForVSETVLI(const MachineInstr &MI,
890889
if (AVLReg == RISCV::X0)
891890
NewInfo.setAVLVLMAX();
892891
else
893-
NewInfo.setAVLDefMI(MRI.getVRegDef(AVLReg));
892+
NewInfo.setAVLReg(AVLReg, MRI.getVRegDef(AVLReg));
894893
}
895894
NewInfo.setVTYPE(MI.getOperand(2).getImm());
896895

@@ -962,9 +961,9 @@ static VSETVLIInfo computeInfoForInstr(const MachineInstr &MI, uint64_t TSFlags,
962961
else
963962
InstrInfo.setAVLImm(Imm);
964963
} else {
965-
InstrInfo.setAVLReg(VLOp.getReg());
966-
if (VLOp.getReg().isVirtual())
967-
InstrInfo.setAVLDefMI(MRI->getVRegDef(VLOp.getReg()));
964+
InstrInfo.setAVLReg(VLOp.getReg(), VLOp.getReg().isVirtual()
965+
? MRI->getVRegDef(VLOp.getReg())
966+
: nullptr);
968967
}
969968
} else {
970969
assert(isScalarExtractInstr(MI));
@@ -1239,9 +1238,10 @@ void RISCVInsertVSETVLI::transferAfter(VSETVLIInfo &Info,
12391238

12401239
if (RISCV::isFaultFirstLoad(MI)) {
12411240
// Update AVL to vl-output of the fault first load.
1242-
Info.setAVLReg(MI.getOperand(1).getReg());
1243-
if (MI.getOperand(1).getReg().isVirtual())
1244-
Info.setAVLDefMI(MRI->getVRegDef(MI.getOperand(1).getReg()));
1241+
Info.setAVLReg(MI.getOperand(1).getReg(),
1242+
MI.getOperand(1).getReg().isVirtual()
1243+
? MRI->getVRegDef(MI.getOperand(1).getReg())
1244+
: nullptr);
12451245
return;
12461246
}
12471247

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