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llvm/lib/Target/X86/X86InstrAMX.td

Lines changed: 11 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -14,40 +14,41 @@
1414
//===----------------------------------------------------------------------===//
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// AMX instructions
1616

17-
multiclass AMX_TILE_COMMON<string Suffix>{
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multiclass AMX_TILE_COMMON<string Suffix, Predicate HasEGPR> {
18+
let Predicates = [HasAMXTILE, HasEGPR, In64BitMode],
19+
OpEnc = !if(!eq(Suffix, ""), EncVEX, EncEVEX), CD8_Scale = 0 in {
1820
let hasSideEffects = 1,
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Defs = [TMM0,TMM1,TMM2,TMM3,TMM4,TMM5,TMM6,TMM7] in
2022
def LDTILECFG#Suffix : I<0x49, MRM0m, (outs), (ins opaquemem:$src),
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"ldtilecfg\t$src",
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[(int_x86_ldtilecfg addr:$src)]>,
23-
VEX, T8, PS;
25+
T8, PS;
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let hasSideEffects = 1 in
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def STTILECFG#Suffix : I<0x49, MRM0m, (outs), (ins opaquemem:$src),
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"sttilecfg\t$src",
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[(int_x86_sttilecfg addr:$src)]>,
28-
VEX, T8, PD;
30+
T8, PD;
2931
let mayLoad = 1 in
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def TILELOADD#Suffix : I<0x4b, MRMSrcMemFSIB, (outs TILE:$dst),
3133
(ins sibmem:$src),
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"tileloadd\t{$src, $dst|$dst, $src}", []>,
33-
VEX, T8, XD;
35+
T8, XD;
3436
let mayLoad = 1 in
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def TILELOADDT1#Suffix : I<0x4b, MRMSrcMemFSIB, (outs TILE:$dst),
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(ins sibmem:$src),
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"tileloaddt1\t{$src, $dst|$dst, $src}", []>,
38-
VEX, T8, PD;
40+
T8, PD;
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let mayStore = 1 in
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def TILESTORED#Suffix : I<0x4b, MRMDestMemFSIB, (outs),
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(ins sibmem:$dst, TILE:$src),
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"tilestored\t{$src, $dst|$dst, $src}", []>,
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VEX, T8, XS;
45+
T8, XS;
46+
}
4447
}
4548

4649
let SchedRW = [WriteSystem] in {
47-
let Predicates = [HasAMXTILE, NoEGPR, In64BitMode] in
48-
defm "" : AMX_TILE_COMMON<"">;
49-
let Predicates = [HasAMXTILE, HasEGPR, In64BitMode] in
50-
defm "" : AMX_TILE_COMMON<"_EVEX">, EVEX, NoCD8;
50+
defm "" : AMX_TILE_COMMON<"", NoEGPR>;
51+
defm "" : AMX_TILE_COMMON<"_EVEX", HasEGPR>;
5152

5253
let Predicates = [HasAMXTILE, In64BitMode] in {
5354
let Defs = [TMM0,TMM1,TMM2,TMM3,TMM4,TMM5,TMM6,TMM7] in

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