@@ -16,13 +16,13 @@ def SDT_LoongArchVreplve : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisVec<0>,
16
16
def SDT_LoongArchVecCond : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVec<1>]>;
17
17
18
18
def SDT_LoongArchVShuf : SDTypeProfile<1, 3, [SDTCisVec<0>,
19
- SDTCisInt<1>, SDTCisVec<1>,
20
- SDTCisSameAs<0, 2>,
21
- SDTCisSameAs<2, 3>]>;
19
+ SDTCisInt<1>, SDTCisVec<1>,
20
+ SDTCisSameAs<0, 2>,
21
+ SDTCisSameAs<2, 3>]>;
22
22
def SDT_LoongArchV2R : SDTypeProfile<1, 2, [SDTCisVec<0>,
23
- SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>]>;
24
- def SDT_loongArchV1RUimm : SDTypeProfile<1, 2, [SDTCisVec<0>,
25
- SDTCisSameAs<0,1>, SDTCisVT<2, i64>]>;
23
+ SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>]>;
24
+ def SDT_LoongArchV1RUimm : SDTypeProfile<1, 2, [SDTCisVec<0>,
25
+ SDTCisSameAs<0,1>, SDTCisVT<2, i64>]>;
26
26
27
27
// Target nodes.
28
28
def loongarch_vreplve : SDNode<"LoongArchISD::VREPLVE", SDT_LoongArchVreplve>;
@@ -31,9 +31,9 @@ def loongarch_vall_nonzero : SDNode<"LoongArchISD::VALL_NONZERO",
31
31
def loongarch_vany_nonzero : SDNode<"LoongArchISD::VANY_NONZERO",
32
32
SDT_LoongArchVecCond>;
33
33
def loongarch_vall_zero : SDNode<"LoongArchISD::VALL_ZERO",
34
- SDT_LoongArchVecCond>;
34
+ SDT_LoongArchVecCond>;
35
35
def loongarch_vany_zero : SDNode<"LoongArchISD::VANY_ZERO",
36
- SDT_LoongArchVecCond>;
36
+ SDT_LoongArchVecCond>;
37
37
38
38
def loongarch_vpick_sext_elt : SDNode<"LoongArchISD::VPICK_SEXT_ELT",
39
39
SDTypeProfile<1, 3, [SDTCisPtrTy<2>]>>;
@@ -48,8 +48,8 @@ def loongarch_vpackod: SDNode<"LoongArchISD::VPACKOD", SDT_LoongArchV2R>;
48
48
def loongarch_vilvl: SDNode<"LoongArchISD::VILVL", SDT_LoongArchV2R>;
49
49
def loongarch_vilvh: SDNode<"LoongArchISD::VILVH", SDT_LoongArchV2R>;
50
50
51
- def loongarch_vshuf4i: SDNode<"LoongArchISD::VSHUF4I", SDT_loongArchV1RUimm >;
52
- def loongarch_vreplvei: SDNode<"LoongArchISD::VREPLVEI", SDT_loongArchV1RUimm >;
51
+ def loongarch_vshuf4i: SDNode<"LoongArchISD::VSHUF4I", SDT_LoongArchV1RUimm >;
52
+ def loongarch_vreplvei: SDNode<"LoongArchISD::VREPLVEI", SDT_LoongArchV1RUimm >;
53
53
54
54
def immZExt1 : ImmLeaf<i64, [{return isUInt<1>(Imm);}]>;
55
55
def immZExt2 : ImmLeaf<i64, [{return isUInt<2>(Imm);}]>;
0 commit comments