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DavidSpickettDavidSpickett
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Revert "[AArch64][GlobalISel] Adopt dup(load) -> LD1R patterns from SelectionDAG"
This reverts commit fb8f591 and b8e9450. Due to test suite failures on AArch64: https://lab.llvm.org/buildbot/#/builders/183/builds/16057
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-32
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4 files changed

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‎llvm/lib/Target/AArch64/AArch64InstrGISel.td

Lines changed: 0 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -496,20 +496,3 @@ let AddedComplexity = 19 in {
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defm : VecROStoreLane64_0Pat<ro16, store, v4i16, i16, hsub, STRHroW, STRHroX>;
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defm : VecROStoreLane64_0Pat<ro32, store, v2i32, i32, ssub, STRSroW, STRSroX>;
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}
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def : Pat<(v8i8 (AArch64dup (i8 (load (am_indexed8 GPR64sp:$Rn))))),
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(LD1Rv8b GPR64sp:$Rn)>;
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def : Pat<(v16i8 (AArch64dup (i8 (load GPR64sp:$Rn)))),
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(LD1Rv16b GPR64sp:$Rn)>;
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def : Pat<(v4i16 (AArch64dup (i16 (load GPR64sp:$Rn)))),
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(LD1Rv4h GPR64sp:$Rn)>;
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def : Pat<(v8i16 (AArch64dup (i16 (load GPR64sp:$Rn)))),
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(LD1Rv8h GPR64sp:$Rn)>;
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def : Pat<(v2i32 (AArch64dup (i32 (load GPR64sp:$Rn)))),
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(LD1Rv2s GPR64sp:$Rn)>;
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def : Pat<(v4i32 (AArch64dup (i32 (load GPR64sp:$Rn)))),
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(LD1Rv4s GPR64sp:$Rn)>;
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def : Pat<(v2i64 (AArch64dup (i64 (load GPR64sp:$Rn)))),
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(LD1Rv2d GPR64sp:$Rn)>;
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def : Pat<(v1i64 (AArch64dup (i64 (load GPR64sp:$Rn)))),
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(LD1Rv1d GPR64sp:$Rn)>;

‎llvm/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll

Lines changed: 12 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
22
; RUN: llc -mtriple=arm64-apple-ios7.0 -o - %s | FileCheck %s --check-prefix=CHECK
3-
; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=arm64-apple-ios7.0 -o - %s 2>&1 | FileCheck %s --check-prefix=CHECK-GISEL
3+
; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=arm64-apple-ios7.0 -o - %s | FileCheck %s --check-prefix=CHECK-GISEL
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; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i8_pre_load
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; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i8_post_load
@@ -620,6 +620,9 @@
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; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for load_single_extract_variable_index_i8
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; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for load_single_extract_variable_index_i16
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; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for load_single_extract_variable_index_i32
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; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for load_single_extract_variable_index_v3i32_small_align
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; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for load_single_extract_variable_index_v3i32_default_align
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; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for load_single_extract_valid_const_index_v3i32
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; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for load_single_extract_variable_index_masked_i32
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; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for load_single_extract_variable_index_masked2_i32
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@@ -13791,9 +13794,8 @@ define <16 x i8> @test_v16i8_post_imm_ld1r(ptr %bar, ptr %ptr) {
1379113794
;
1379213795
; CHECK-GISEL-LABEL: test_v16i8_post_imm_ld1r:
1379313796
; CHECK-GISEL: ; %bb.0:
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; CHECK-GISEL-NEXT: ld1r.16b { v0 }, [x0]
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; CHECK-GISEL-NEXT: add x8, x0, #1
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; CHECK-GISEL-NEXT: str x8, [x1]
13797+
; CHECK-GISEL-NEXT: ld1r.16b { v0 }, [x0], #1
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; CHECK-GISEL-NEXT: str x0, [x1]
1379713799
; CHECK-GISEL-NEXT: ret
1379813800
%tmp1 = load i8, ptr %bar
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%tmp2 = insertelement <16 x i8> <i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>, i8 %tmp1, i32 0
@@ -13826,9 +13828,8 @@ define <16 x i8> @test_v16i8_post_reg_ld1r(ptr %bar, ptr %ptr, i64 %inc) {
1382613828
;
1382713829
; CHECK-GISEL-LABEL: test_v16i8_post_reg_ld1r:
1382813830
; CHECK-GISEL: ; %bb.0:
13829-
; CHECK-GISEL-NEXT: ld1r.16b { v0 }, [x0]
13830-
; CHECK-GISEL-NEXT: add x8, x0, x2
13831-
; CHECK-GISEL-NEXT: str x8, [x1]
13831+
; CHECK-GISEL-NEXT: ld1r.16b { v0 }, [x0], x2
13832+
; CHECK-GISEL-NEXT: str x0, [x1]
1383213833
; CHECK-GISEL-NEXT: ret
1383313834
%tmp1 = load i8, ptr %bar
1383413835
%tmp2 = insertelement <16 x i8> <i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>, i8 %tmp1, i32 0
@@ -13861,9 +13862,8 @@ define <8 x i8> @test_v8i8_post_imm_ld1r(ptr %bar, ptr %ptr) {
1386113862
;
1386213863
; CHECK-GISEL-LABEL: test_v8i8_post_imm_ld1r:
1386313864
; CHECK-GISEL: ; %bb.0:
13864-
; CHECK-GISEL-NEXT: ld1r.8b { v0 }, [x0]
13865-
; CHECK-GISEL-NEXT: add x8, x0, #1
13866-
; CHECK-GISEL-NEXT: str x8, [x1]
13865+
; CHECK-GISEL-NEXT: ld1r.8b { v0 }, [x0], #1
13866+
; CHECK-GISEL-NEXT: str x0, [x1]
1386713867
; CHECK-GISEL-NEXT: ret
1386813868
%tmp1 = load i8, ptr %bar
1386913869
%tmp2 = insertelement <8 x i8> <i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>, i8 %tmp1, i32 0
@@ -13888,9 +13888,8 @@ define <8 x i8> @test_v8i8_post_reg_ld1r(ptr %bar, ptr %ptr, i64 %inc) {
1388813888
;
1388913889
; CHECK-GISEL-LABEL: test_v8i8_post_reg_ld1r:
1389013890
; CHECK-GISEL: ; %bb.0:
13891-
; CHECK-GISEL-NEXT: ld1r.8b { v0 }, [x0]
13892-
; CHECK-GISEL-NEXT: add x8, x0, x2
13893-
; CHECK-GISEL-NEXT: str x8, [x1]
13891+
; CHECK-GISEL-NEXT: ld1r.8b { v0 }, [x0], x2
13892+
; CHECK-GISEL-NEXT: str x0, [x1]
1389413893
; CHECK-GISEL-NEXT: ret
1389513894
%tmp1 = load i8, ptr %bar
1389613895
%tmp2 = insertelement <8 x i8> <i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>, i8 %tmp1, i32 0

‎llvm/test/CodeGen/AArch64/arm64-ld1.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
22
; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-SD
3-
; RUN: llc < %s -global-isel=1 -global-isel-abort=1 -mtriple=arm64-eabi -aarch64-neon-syntax=apple -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-GI
3+
; RUN: llc < %s -global-isel=1 -global-isel-abort=2 -mtriple=arm64-eabi -aarch64-neon-syntax=apple -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-GI
44

55
%struct.__neon_int8x8x2_t = type { <8 x i8>, <8 x i8> }
66
%struct.__neon_int8x8x3_t = type { <8 x i8>, <8 x i8>, <8 x i8> }

‎llvm/test/CodeGen/AArch64/arm64-st1.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -verify-machineinstrs | FileCheck %s
2-
; RUN: llc < %s -global-isel -global-isel-abort=1 -mtriple=arm64-eabi -aarch64-neon-syntax=apple -verify-machineinstrs | FileCheck %s
2+
; RUN: llc < %s -global-isel -mtriple=arm64-eabi -aarch64-neon-syntax=apple -verify-machineinstrs | FileCheck %s
33
; The instruction latencies of Exynos-M3 trigger the transform we see under the Exynos check.
44
; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -verify-machineinstrs -mcpu=exynos-m3 | FileCheck --check-prefix=EXYNOS %s
55

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