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paulwalker-armpaulwalker-arm
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[LLVM][SVE] Move ADDVL isel patterns under UseScalarIncVL feature flag. (#71173)
Also removes a duplicate pattern.
1 parent 05a4770 commit 17970df

13 files changed

+65
-58
lines changed

‎llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td

Lines changed: 8 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -2423,14 +2423,6 @@ let Predicates = [HasSVEorSME] in {
24232423
}
24242424

24252425
let AddedComplexity = 5 in {
2426-
def : Pat<(add GPR64:$op, (vscale (sve_rdvl_imm i32:$imm))),
2427-
(ADDVL_XXI GPR64:$op, $imm)>;
2428-
2429-
def : Pat<(add GPR32:$op, (i32 (trunc (vscale (sve_rdvl_imm i32:$imm))))),
2430-
(i32 (EXTRACT_SUBREG (ADDVL_XXI (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
2431-
GPR32:$op, sub_32), $imm),
2432-
sub_32))>;
2433-
24342426
def : Pat<(nxv8i16 (add ZPR:$op, (nxv8i16 (splat_vector (i32 (trunc (vscale (sve_cnth_imm i32:$imm)))))))),
24352427
(INCH_ZPiI ZPR:$op, 31, $imm)>;
24362428
def : Pat<(nxv4i32 (add ZPR:$op, (nxv4i32 (splat_vector (i32 (trunc (vscale (sve_cntw_imm i32:$imm)))))))),
@@ -2447,6 +2439,14 @@ let Predicates = [HasSVEorSME] in {
24472439
}
24482440

24492441
let Predicates = [HasSVEorSME, UseScalarIncVL], AddedComplexity = 5 in {
2442+
def : Pat<(add GPR64:$op, (vscale (sve_rdvl_imm i32:$imm))),
2443+
(ADDVL_XXI GPR64:$op, $imm)>;
2444+
2445+
def : Pat<(add GPR32:$op, (i32 (trunc (vscale (sve_rdvl_imm i32:$imm))))),
2446+
(i32 (EXTRACT_SUBREG (ADDVL_XXI (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
2447+
GPR32:$op, sub_32), $imm),
2448+
sub_32))>;
2449+
24502450
def : Pat<(add GPR64:$op, (vscale (sve_cnth_imm i32:$imm))),
24512451
(INCH_XPiI GPR64:$op, 31, $imm)>;
24522452
def : Pat<(add GPR64:$op, (vscale (sve_cntw_imm i32:$imm))),
@@ -2488,9 +2488,6 @@ let Predicates = [HasSVEorSME] in {
24882488
sub_32))>;
24892489
}
24902490

2491-
def : Pat<(add GPR64:$op, (vscale (sve_rdvl_imm i32:$imm))),
2492-
(ADDVL_XXI GPR64:$op, $imm)>;
2493-
24942491
// FIXME: BigEndian requires an additional REV instruction to satisfy the
24952492
// constraint that none of the bits change when stored to memory as one
24962493
// type, and reloaded as another type.

‎llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions-scalable.ll

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -195,13 +195,14 @@ define %"class.std::complex" @complex_mul_v2f64_unrolled(ptr %a, ptr %b) {
195195
; CHECK-NEXT: ptrue p0.d
196196
; CHECK-NEXT: neg x10, x9
197197
; CHECK-NEXT: mov w11, #1000 // =0x3e8
198+
; CHECK-NEXT: rdvl x13, #2
198199
; CHECK-NEXT: mov x8, xzr
199200
; CHECK-NEXT: and x10, x10, x11
200-
; CHECK-NEXT: rdvl x11, #4
201201
; CHECK-NEXT: zip2 z0.d, z1.d, z1.d
202202
; CHECK-NEXT: zip1 z1.d, z1.d, z1.d
203-
; CHECK-NEXT: addvl x12, x1, #2
204-
; CHECK-NEXT: addvl x13, x0, #2
203+
; CHECK-NEXT: rdvl x11, #4
204+
; CHECK-NEXT: add x12, x1, x13
205+
; CHECK-NEXT: add x13, x0, x13
205206
; CHECK-NEXT: mov z2.d, z1.d
206207
; CHECK-NEXT: mov z3.d, z0.d
207208
; CHECK-NEXT: .LBB2_1: // %vector.body

‎llvm/test/CodeGen/AArch64/named-vector-shuffles-sve.ll

Lines changed: 11 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -351,9 +351,9 @@ define <vscale x 16 x float> @splice_nxv16f32_16(<vscale x 16 x float> %a, <vsca
351351
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
352352
; CHECK-NEXT: addvl sp, sp, #-8
353353
; CHECK-NEXT: ptrue p0.s
354-
; CHECK-NEXT: mov x8, #-1 // =0xffffffffffffffff
354+
; CHECK-NEXT: rdvl x8, #1
355355
; CHECK-NEXT: mov w9, #16 // =0x10
356-
; CHECK-NEXT: addvl x8, x8, #1
356+
; CHECK-NEXT: sub x8, x8, #1
357357
; CHECK-NEXT: cmp x8, #16
358358
; CHECK-NEXT: csel x8, x8, x9, lo
359359
; CHECK-NEXT: mov x9, sp
@@ -457,7 +457,7 @@ define <vscale x 16 x i8> @splice_nxv16i8_neg17(<vscale x 16 x i8> %a, <vscale x
457457
; CHECK-NEXT: mov w9, #17 // =0x11
458458
; CHECK-NEXT: mov x10, sp
459459
; CHECK-NEXT: cmp x8, #17
460-
; CHECK-NEXT: addvl x10, x10, #1
460+
; CHECK-NEXT: add x10, x10, x8
461461
; CHECK-NEXT: csel x8, x8, x9, lo
462462
; CHECK-NEXT: sub x8, x10, x8
463463
; CHECK-NEXT: st1b { z0.b }, p0, [sp]
@@ -502,7 +502,7 @@ define <vscale x 8 x i16> @splice_nxv8i16_neg9(<vscale x 8 x i16> %a, <vscale x
502502
; CHECK-NEXT: mov w9, #18 // =0x12
503503
; CHECK-NEXT: mov x10, sp
504504
; CHECK-NEXT: cmp x8, #18
505-
; CHECK-NEXT: addvl x10, x10, #1
505+
; CHECK-NEXT: add x10, x10, x8
506506
; CHECK-NEXT: csel x8, x8, x9, lo
507507
; CHECK-NEXT: sub x8, x10, x8
508508
; CHECK-NEXT: st1h { z0.h }, p0, [sp]
@@ -613,7 +613,7 @@ define <vscale x 8 x half> @splice_nxv8f16_neg9(<vscale x 8 x half> %a, <vscale
613613
; CHECK-NEXT: mov w9, #18 // =0x12
614614
; CHECK-NEXT: mov x10, sp
615615
; CHECK-NEXT: cmp x8, #18
616-
; CHECK-NEXT: addvl x10, x10, #1
616+
; CHECK-NEXT: add x10, x10, x8
617617
; CHECK-NEXT: csel x8, x8, x9, lo
618618
; CHECK-NEXT: sub x8, x10, x8
619619
; CHECK-NEXT: st1h { z0.h }, p0, [sp]
@@ -779,9 +779,10 @@ define <vscale x 8 x i32> @splice_nxv8i32(<vscale x 8 x i32> %a, <vscale x 8 x i
779779
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
780780
; CHECK-NEXT: addvl sp, sp, #-4
781781
; CHECK-NEXT: ptrue p0.s
782-
; CHECK-NEXT: mov x8, sp
782+
; CHECK-NEXT: rdvl x8, #2
783+
; CHECK-NEXT: mov x9, sp
784+
; CHECK-NEXT: add x8, x9, x8
783785
; CHECK-NEXT: mov x9, #-8 // =0xfffffffffffffff8
784-
; CHECK-NEXT: addvl x8, x8, #2
785786
; CHECK-NEXT: sub x10, x8, #32
786787
; CHECK-NEXT: st1w { z1.s }, p0, [sp, #1, mul vl]
787788
; CHECK-NEXT: st1w { z0.s }, p0, [sp]
@@ -807,9 +808,9 @@ define <vscale x 16 x float> @splice_nxv16f32_neg17(<vscale x 16 x float> %a, <v
807808
; CHECK-NEXT: mov w9, #68 // =0x44
808809
; CHECK-NEXT: mov x10, sp
809810
; CHECK-NEXT: cmp x8, #68
810-
; CHECK-NEXT: csel x8, x8, x9, lo
811-
; CHECK-NEXT: addvl x9, x10, #4
812-
; CHECK-NEXT: sub x8, x9, x8
811+
; CHECK-NEXT: csel x9, x8, x9, lo
812+
; CHECK-NEXT: add x8, x10, x8
813+
; CHECK-NEXT: sub x8, x8, x9
813814
; CHECK-NEXT: st1w { z3.s }, p0, [sp, #3, mul vl]
814815
; CHECK-NEXT: st1w { z2.s }, p0, [sp, #2, mul vl]
815816
; CHECK-NEXT: st1w { z1.s }, p0, [sp, #1, mul vl]

‎llvm/test/CodeGen/AArch64/sve-extract-fixed-vector.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -215,9 +215,9 @@ define <16 x i8> @extract_v16i8_nxv16i8_idx16(<vscale x 16 x i8> %vec) nounwind
215215
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
216216
; CHECK-NEXT: addvl sp, sp, #-1
217217
; CHECK-NEXT: ptrue p0.b
218-
; CHECK-NEXT: mov x8, #-16 // =0xfffffffffffffff0
218+
; CHECK-NEXT: rdvl x8, #1
219219
; CHECK-NEXT: mov w9, #16 // =0x10
220-
; CHECK-NEXT: addvl x8, x8, #1
220+
; CHECK-NEXT: sub x8, x8, #16
221221
; CHECK-NEXT: cmp x8, #16
222222
; CHECK-NEXT: csel x8, x8, x9, lo
223223
; CHECK-NEXT: mov x9, sp

‎llvm/test/CodeGen/AArch64/sve-gep.ll

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,8 @@
44
define <vscale x 2 x i64>* @scalar_of_scalable_1(<vscale x 2 x i64>* %base) {
55
; CHECK-LABEL: scalar_of_scalable_1:
66
; CHECK: // %bb.0:
7-
; CHECK-NEXT: addvl x0, x0, #4
7+
; CHECK-NEXT: rdvl x8, #4
8+
; CHECK-NEXT: add x0, x0, x8
89
; CHECK-NEXT: ret
910
%d = getelementptr <vscale x 2 x i64>, <vscale x 2 x i64>* %base, i64 4
1011
ret <vscale x 2 x i64>* %d
@@ -202,7 +203,8 @@ define <vscale x 2 x i64*> @scalable_of_fixed_5_i64(i64* %base, <vscale x 2 x i3
202203
define <vscale x 2 x <vscale x 2 x i64>*> @scalable_of_scalable_1(<vscale x 2 x i64>* %base) {
203204
; CHECK-LABEL: scalable_of_scalable_1:
204205
; CHECK: // %bb.0:
205-
; CHECK-NEXT: addvl x8, x0, #1
206+
; CHECK-NEXT: rdvl x8, #1
207+
; CHECK-NEXT: add x8, x0, x8
206208
; CHECK-NEXT: mov z0.d, x8
207209
; CHECK-NEXT: ret
208210
%idx = shufflevector <vscale x 2 x i64> insertelement (<vscale x 2 x i64> undef, i64 1, i32 0), <vscale x 2 x i64> zeroinitializer, <vscale x 2 x i32> zeroinitializer

‎llvm/test/CodeGen/AArch64/sve-insert-element.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -590,10 +590,10 @@ define <vscale x 32 x i1> @test_predicate_insert_32xi1(<vscale x 32 x i1> %val,
590590
; CHECK-NEXT: addvl sp, sp, #-2
591591
; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 16 * VG
592592
; CHECK-NEXT: ptrue p2.b
593-
; CHECK-NEXT: mov x8, #-1 // =0xffffffffffffffff
593+
; CHECK-NEXT: rdvl x8, #2
594594
; CHECK-NEXT: mov z0.b, p1/z, #1 // =0x1
595595
; CHECK-NEXT: mov z1.b, p0/z, #1 // =0x1
596-
; CHECK-NEXT: addvl x8, x8, #2
596+
; CHECK-NEXT: sub x8, x8, #1
597597
; CHECK-NEXT: mov w9, w1
598598
; CHECK-NEXT: cmp x9, x8
599599
; CHECK-NEXT: csel x8, x9, x8, lo

‎llvm/test/CodeGen/AArch64/sve-insert-vector.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -120,9 +120,9 @@ define <vscale x 16 x i8> @insert_v16i8_nxv16i8_idx16(<vscale x 16 x i8> %vec, <
120120
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
121121
; CHECK-NEXT: addvl sp, sp, #-1
122122
; CHECK-NEXT: ptrue p0.b
123-
; CHECK-NEXT: mov x8, #-16 // =0xfffffffffffffff0
123+
; CHECK-NEXT: rdvl x8, #1
124124
; CHECK-NEXT: mov w9, #16 // =0x10
125-
; CHECK-NEXT: addvl x8, x8, #1
125+
; CHECK-NEXT: sub x8, x8, #16
126126
; CHECK-NEXT: mov x10, sp
127127
; CHECK-NEXT: cmp x8, #16
128128
; CHECK-NEXT: csel x8, x8, x9, lo

‎llvm/test/CodeGen/AArch64/sve-intrinsics-loads-nf.ll

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -17,7 +17,8 @@ define <vscale x 16 x i8> @ldnf1b(<vscale x 16 x i1> %pg, ptr %a) {
1717
define <vscale x 16 x i8> @ldnf1b_out_of_lower_bound(<vscale x 16 x i1> %pg, ptr %a) {
1818
; CHECK-LABEL: ldnf1b_out_of_lower_bound:
1919
; CHECK: // %bb.0:
20-
; CHECK-NEXT: addvl x8, x0, #-9
20+
; CHECK-NEXT: rdvl x8, #-9
21+
; CHECK-NEXT: add x8, x0, x8
2122
; CHECK-NEXT: ldnf1b { z0.b }, p0/z, [x8]
2223
; CHECK-NEXT: ret
2324
%base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %a, i64 -9
@@ -62,7 +63,8 @@ define <vscale x 16 x i8> @ldnf1b_upper_bound(<vscale x 16 x i1> %pg, ptr %a) {
6263
define <vscale x 16 x i8> @ldnf1b_out_of_upper_bound(<vscale x 16 x i1> %pg, ptr %a) {
6364
; CHECK-LABEL: ldnf1b_out_of_upper_bound:
6465
; CHECK: // %bb.0:
65-
; CHECK-NEXT: addvl x8, x0, #8
66+
; CHECK-NEXT: rdvl x8, #8
67+
; CHECK-NEXT: add x8, x0, x8
6668
; CHECK-NEXT: ldnf1b { z0.b }, p0/z, [x8]
6769
; CHECK-NEXT: ret
6870
%base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %a, i64 8

‎llvm/test/CodeGen/AArch64/sve-pred-contiguous-ldst-addressing-mode-reg-imm.ll

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -9,9 +9,11 @@
99
define void @imm_out_of_range(<vscale x 2 x i64> * %base, <vscale x 2 x i1> %mask) nounwind {
1010
; CHECK-LABEL: imm_out_of_range:
1111
; CHECK: // %bb.0:
12-
; CHECK-NEXT: addvl x8, x0, #8
12+
; CHECK-NEXT: rdvl x8, #8
13+
; CHECK-NEXT: add x8, x0, x8
1314
; CHECK-NEXT: ld1d { z0.d }, p0/z, [x8]
14-
; CHECK-NEXT: addvl x8, x0, #-9
15+
; CHECK-NEXT: rdvl x8, #-9
16+
; CHECK-NEXT: add x8, x0, x8
1517
; CHECK-NEXT: st1d { z0.d }, p0, [x8]
1618
; CHECK-NEXT: ret
1719
%base_load = getelementptr <vscale x 2 x i64>, <vscale x 2 x i64>* %base, i64 8

‎llvm/test/CodeGen/AArch64/sve-pred-non-temporal-ldst-addressing-mode-reg-imm.ll

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -9,9 +9,11 @@
99
define void @imm_out_of_range(<vscale x 2 x i64> * %base, <vscale x 2 x i1> %mask) nounwind {
1010
; CHECK-LABEL: imm_out_of_range:
1111
; CHECK: // %bb.0:
12-
; CHECK-NEXT: addvl x8, x0, #8
12+
; CHECK-NEXT: rdvl x8, #8
13+
; CHECK-NEXT: add x8, x0, x8
1314
; CHECK-NEXT: ldnt1d { z0.d }, p0/z, [x8]
14-
; CHECK-NEXT: addvl x8, x0, #-9
15+
; CHECK-NEXT: rdvl x8, #-9
16+
; CHECK-NEXT: add x8, x0, x8
1517
; CHECK-NEXT: stnt1d { z0.d }, p0, [x8]
1618
; CHECK-NEXT: ret
1719
%base_load = getelementptr <vscale x 2 x i64>, <vscale x 2 x i64>* %base, i64 8

‎llvm/test/CodeGen/AArch64/sve-split-extract-elt.ll

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -23,9 +23,9 @@ define i8 @split_extract_32i8_idx(<vscale x 32 x i8> %a, i32 %idx) {
2323
; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 16 * VG
2424
; CHECK-NEXT: .cfi_offset w29, -16
2525
; CHECK-NEXT: ptrue p0.b
26-
; CHECK-NEXT: mov x8, #-1 // =0xffffffffffffffff
26+
; CHECK-NEXT: rdvl x8, #2
2727
; CHECK-NEXT: mov w9, w0
28-
; CHECK-NEXT: addvl x8, x8, #2
28+
; CHECK-NEXT: sub x8, x8, #1
2929
; CHECK-NEXT: cmp x9, x8
3030
; CHECK-NEXT: csel x8, x9, x8, lo
3131
; CHECK-NEXT: mov x9, sp
@@ -47,9 +47,9 @@ define i16 @split_extract_16i16_idx(<vscale x 16 x i16> %a, i32 %idx) {
4747
; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 16 * VG
4848
; CHECK-NEXT: .cfi_offset w29, -16
4949
; CHECK-NEXT: ptrue p0.h
50-
; CHECK-NEXT: mov x8, #-1 // =0xffffffffffffffff
50+
; CHECK-NEXT: rdvl x8, #1
5151
; CHECK-NEXT: mov w9, w0
52-
; CHECK-NEXT: addvl x8, x8, #1
52+
; CHECK-NEXT: sub x8, x8, #1
5353
; CHECK-NEXT: cmp x9, x8
5454
; CHECK-NEXT: csel x8, x9, x8, lo
5555
; CHECK-NEXT: mov x9, sp
@@ -141,9 +141,9 @@ define i16 @split_extract_16i16(<vscale x 16 x i16> %a) {
141141
; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 16 * VG
142142
; CHECK-NEXT: .cfi_offset w29, -16
143143
; CHECK-NEXT: ptrue p0.h
144-
; CHECK-NEXT: mov x8, #-1 // =0xffffffffffffffff
144+
; CHECK-NEXT: rdvl x8, #1
145145
; CHECK-NEXT: mov w9, #128 // =0x80
146-
; CHECK-NEXT: addvl x8, x8, #1
146+
; CHECK-NEXT: sub x8, x8, #1
147147
; CHECK-NEXT: cmp x8, #128
148148
; CHECK-NEXT: csel x8, x8, x9, lo
149149
; CHECK-NEXT: mov x9, sp
@@ -165,10 +165,10 @@ define i32 @split_extract_16i32(<vscale x 16 x i32> %a) {
165165
; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 32 * VG
166166
; CHECK-NEXT: .cfi_offset w29, -16
167167
; CHECK-NEXT: ptrue p0.s
168-
; CHECK-NEXT: mov x8, #-1 // =0xffffffffffffffff
168+
; CHECK-NEXT: rdvl x8, #1
169169
; CHECK-NEXT: mov w9, #34464 // =0x86a0
170170
; CHECK-NEXT: movk w9, #1, lsl #16
171-
; CHECK-NEXT: addvl x8, x8, #1
171+
; CHECK-NEXT: sub x8, x8, #1
172172
; CHECK-NEXT: cmp x8, x9
173173
; CHECK-NEXT: csel x8, x8, x9, lo
174174
; CHECK-NEXT: mov x9, sp

‎llvm/test/CodeGen/AArch64/sve-split-insert-elt.ll

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -24,9 +24,9 @@ define <vscale x 32 x i8> @split_insert_32i8_idx(<vscale x 32 x i8> %a, i8 %elt,
2424
; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 16 * VG
2525
; CHECK-NEXT: .cfi_offset w29, -16
2626
; CHECK-NEXT: ptrue p0.b
27-
; CHECK-NEXT: mov x8, #-1 // =0xffffffffffffffff
27+
; CHECK-NEXT: rdvl x8, #2
2828
; CHECK-NEXT: mov x9, sp
29-
; CHECK-NEXT: addvl x8, x8, #2
29+
; CHECK-NEXT: sub x8, x8, #1
3030
; CHECK-NEXT: cmp x1, x8
3131
; CHECK-NEXT: csel x8, x1, x8, lo
3232
; CHECK-NEXT: st1b { z1.b }, p0, [sp, #1, mul vl]
@@ -136,9 +136,9 @@ define <vscale x 32 x i16> @split_insert_32i16(<vscale x 32 x i16> %a, i16 %elt)
136136
; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 32 * VG
137137
; CHECK-NEXT: .cfi_offset w29, -16
138138
; CHECK-NEXT: ptrue p0.h
139-
; CHECK-NEXT: mov x8, #-1 // =0xffffffffffffffff
139+
; CHECK-NEXT: rdvl x8, #2
140140
; CHECK-NEXT: mov w9, #128 // =0x80
141-
; CHECK-NEXT: addvl x8, x8, #2
141+
; CHECK-NEXT: sub x8, x8, #1
142142
; CHECK-NEXT: cmp x8, #128
143143
; CHECK-NEXT: csel x8, x8, x9, lo
144144
; CHECK-NEXT: mov x9, sp

‎llvm/test/CodeGen/AArch64/sve-vl-arith.ll

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -116,7 +116,8 @@ define <vscale x 2 x i64> @decd_vec(<vscale x 2 x i64> %a) {
116116
define i64 @incb_scalar_i64(i64 %a) {
117117
; NO_SCALAR_INC-LABEL: incb_scalar_i64:
118118
; NO_SCALAR_INC: // %bb.0:
119-
; NO_SCALAR_INC-NEXT: addvl x0, x0, #1
119+
; NO_SCALAR_INC-NEXT: rdvl x8, #1
120+
; NO_SCALAR_INC-NEXT: add x0, x0, x8
120121
; NO_SCALAR_INC-NEXT: ret
121122
;
122123
; CHECK-LABEL: incb_scalar_i64:
@@ -185,7 +186,8 @@ define i64 @incd_scalar_i64(i64 %a) {
185186
define i64 @decb_scalar_i64(i64 %a) {
186187
; NO_SCALAR_INC-LABEL: decb_scalar_i64:
187188
; NO_SCALAR_INC: // %bb.0:
188-
; NO_SCALAR_INC-NEXT: addvl x0, x0, #-2
189+
; NO_SCALAR_INC-NEXT: rdvl x8, #-2
190+
; NO_SCALAR_INC-NEXT: add x0, x0, x8
189191
; NO_SCALAR_INC-NEXT: ret
190192
;
191193
; CHECK-LABEL: decb_scalar_i64:
@@ -257,9 +259,8 @@ define i64 @decd_scalar_i64(i64 %a) {
257259
define i32 @incb_scalar_i32(i32 %a) {
258260
; NO_SCALAR_INC-LABEL: incb_scalar_i32:
259261
; NO_SCALAR_INC: // %bb.0:
260-
; NO_SCALAR_INC-NEXT: // kill: def $w0 killed $w0 def $x0
261-
; NO_SCALAR_INC-NEXT: addvl x0, x0, #3
262-
; NO_SCALAR_INC-NEXT: // kill: def $w0 killed $w0 killed $x0
262+
; NO_SCALAR_INC-NEXT: rdvl x8, #3
263+
; NO_SCALAR_INC-NEXT: add w0, w0, w8
263264
; NO_SCALAR_INC-NEXT: ret
264265
;
265266
; CHECK-LABEL: incb_scalar_i32:
@@ -344,9 +345,8 @@ define i32 @incd_scalar_i32(i32 %a) {
344345
define i32 @decb_scalar_i32(i32 %a) {
345346
; NO_SCALAR_INC-LABEL: decb_scalar_i32:
346347
; NO_SCALAR_INC: // %bb.0:
347-
; NO_SCALAR_INC-NEXT: // kill: def $w0 killed $w0 def $x0
348-
; NO_SCALAR_INC-NEXT: addvl x0, x0, #-4
349-
; NO_SCALAR_INC-NEXT: // kill: def $w0 killed $w0 killed $x0
348+
; NO_SCALAR_INC-NEXT: rdvl x8, #-4
349+
; NO_SCALAR_INC-NEXT: add w0, w0, w8
350350
; NO_SCALAR_INC-NEXT: ret
351351
;
352352
; CHECK-LABEL: decb_scalar_i32:

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