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[RISCV] Use tail undisturbed vmv.v.v instead of vslideup.vi vN, vM, 0 for subvector insertion
vslideup has a vector overlap constraint that vmv.v.v doesn't. vmv.v.v is also a simpler instruction so may have better throughput and/or latency in some CPUs. This is an alternative to D152298, D152368, and D152496. Reviewed By: luke, reames Differential Revision: https://reviews.llvm.org/D152565
1 parent 65f6373 commit 17e2d07

15 files changed

+150
-116
lines changed

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 35 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -7386,17 +7386,26 @@ SDValue RISCVTargetLowering::lowerINSERT_SUBVECTOR(SDValue Op,
73867386
// that for slideup this includes the offset.
73877387
unsigned EndIndex = OrigIdx + SubVecVT.getVectorNumElements();
73887388
SDValue VL = getVLOp(EndIndex, DL, DAG, Subtarget);
7389-
SDValue SlideupAmt = DAG.getConstant(OrigIdx, DL, XLenVT);
73907389

73917390
// Use tail agnostic policy if we're inserting over Vec's tail.
73927391
unsigned Policy = RISCVII::TAIL_UNDISTURBED_MASK_UNDISTURBED;
73937392
if (VecVT.isFixedLengthVector() && EndIndex == VecVT.getVectorNumElements())
73947393
Policy = RISCVII::TAIL_AGNOSTIC;
7395-
SDValue Slideup = getVSlideup(DAG, Subtarget, DL, ContainerVT, Vec, SubVec,
7396-
SlideupAmt, Mask, VL, Policy);
7394+
7395+
// If we're inserting into the lowest elements, use a tail undisturbed
7396+
// vmv.v.v.
7397+
if (OrigIdx == 0) {
7398+
SubVec =
7399+
DAG.getNode(RISCVISD::VMV_V_V_VL, DL, ContainerVT, Vec, SubVec, VL);
7400+
} else {
7401+
SDValue SlideupAmt = DAG.getConstant(OrigIdx, DL, XLenVT);
7402+
SubVec = getVSlideup(DAG, Subtarget, DL, ContainerVT, Vec, SubVec,
7403+
SlideupAmt, Mask, VL, Policy);
7404+
}
7405+
73977406
if (VecVT.isFixedLengthVector())
7398-
Slideup = convertFromScalableVector(VecVT, Slideup, DAG, Subtarget);
7399-
return DAG.getBitcast(Op.getValueType(), Slideup);
7407+
SubVec = convertFromScalableVector(VecVT, SubVec, DAG, Subtarget);
7408+
return DAG.getBitcast(Op.getValueType(), SubVec);
74007409
}
74017410

74027411
unsigned SubRegIdx, RemIdx;
@@ -7440,31 +7449,39 @@ SDValue RISCVTargetLowering::lowerINSERT_SUBVECTOR(SDValue Op,
74407449
DAG.getConstant(AlignedIdx, DL, XLenVT));
74417450
}
74427451

7443-
SDValue SlideupAmt =
7444-
DAG.getVScale(DL, XLenVT, APInt(XLenVT.getSizeInBits(), RemIdx));
7452+
SubVec = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, InterSubVT,
7453+
DAG.getUNDEF(InterSubVT), SubVec,
7454+
DAG.getConstant(0, DL, XLenVT));
74457455

74467456
auto [Mask, VL] = getDefaultScalableVLOps(VecVT, DL, DAG, Subtarget);
74477457

7448-
// Construct the vector length corresponding to RemIdx + length(SubVecVT).
74497458
VL = computeVLMax(SubVecVT, DL, DAG);
7450-
VL = DAG.getNode(ISD::ADD, DL, XLenVT, SlideupAmt, VL);
74517459

7452-
SubVec = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, InterSubVT,
7453-
DAG.getUNDEF(InterSubVT), SubVec,
7454-
DAG.getConstant(0, DL, XLenVT));
7460+
// If we're inserting into the lowest elements, use a tail undisturbed
7461+
// vmv.v.v.
7462+
if (RemIdx == 0) {
7463+
SubVec = DAG.getNode(RISCVISD::VMV_V_V_VL, DL, InterSubVT, AlignedExtract,
7464+
SubVec, VL);
7465+
} else {
7466+
SDValue SlideupAmt =
7467+
DAG.getVScale(DL, XLenVT, APInt(XLenVT.getSizeInBits(), RemIdx));
7468+
7469+
// Construct the vector length corresponding to RemIdx + length(SubVecVT).
7470+
VL = DAG.getNode(ISD::ADD, DL, XLenVT, SlideupAmt, VL);
74557471

7456-
SDValue Slideup = getVSlideup(DAG, Subtarget, DL, InterSubVT, AlignedExtract,
7457-
SubVec, SlideupAmt, Mask, VL);
7472+
SubVec = getVSlideup(DAG, Subtarget, DL, InterSubVT, AlignedExtract, SubVec,
7473+
SlideupAmt, Mask, VL);
7474+
}
74587475

74597476
// If required, insert this subvector back into the correct vector register.
74607477
// This should resolve to an INSERT_SUBREG instruction.
74617478
if (VecVT.bitsGT(InterSubVT))
7462-
Slideup = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VecVT, Vec, Slideup,
7463-
DAG.getConstant(AlignedIdx, DL, XLenVT));
7479+
SubVec = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VecVT, Vec, SubVec,
7480+
DAG.getConstant(AlignedIdx, DL, XLenVT));
74647481

74657482
// We might have bitcast from a mask type: cast back to the original type if
74667483
// required.
7467-
return DAG.getBitcast(Op.getSimpleValueType(), Slideup);
7484+
return DAG.getBitcast(Op.getSimpleValueType(), SubVec);
74687485
}
74697486

74707487
SDValue RISCVTargetLowering::lowerEXTRACT_SUBVECTOR(SDValue Op,
@@ -15535,6 +15552,7 @@ const char *RISCVTargetLowering::getTargetNodeName(unsigned Opcode) const {
1553515552
NODE_NAME_CASE(TH_LDD)
1553615553
NODE_NAME_CASE(TH_SWD)
1553715554
NODE_NAME_CASE(TH_SDD)
15555+
NODE_NAME_CASE(VMV_V_V_VL)
1553815556
NODE_NAME_CASE(VMV_V_X_VL)
1553915557
NODE_NAME_CASE(VFMV_V_F_VL)
1554015558
NODE_NAME_CASE(VMV_X_S)

‎llvm/lib/Target/RISCV/RISCVISelLowering.h

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -129,6 +129,10 @@ enum NodeType : unsigned {
129129
ZIP,
130130
UNZIP,
131131
// Vector Extension
132+
// VMV_V_V_VL matches the semantics of vmv.v.v but includes an extra operand
133+
// for the VL value to be used for the operation. The first operand is
134+
// passthru operand.
135+
VMV_V_V_VL,
132136
// VMV_V_X_VL matches the semantics of vmv.v.x but includes an extra operand
133137
// for the VL value to be used for the operation. The first operand is
134138
// passthru operand.

‎llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td

Lines changed: 17 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -50,6 +50,11 @@ def SDT_RISCVCopySign_VL : SDTypeProfile<1, 5, [SDTCisSameAs<0, 1>,
5050
SDTCisSameNumEltsAs<0, 4>,
5151
SDTCisVT<5, XLenVT>]>;
5252

53+
def riscv_vmv_v_v_vl : SDNode<"RISCVISD::VMV_V_V_VL",
54+
SDTypeProfile<1, 3, [SDTCisVec<0>,
55+
SDTCisSameAs<0, 1>,
56+
SDTCisSameAs<0, 2>,
57+
SDTCisVT<3, XLenVT>]>>;
5358
def riscv_vmv_v_x_vl : SDNode<"RISCVISD::VMV_V_X_VL",
5459
SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisInt<0>,
5560
SDTCisSameAs<0, 1>,
@@ -1772,8 +1777,19 @@ foreach vti = AllIntegerVectors in {
17721777
}
17731778

17741779
// 11.16. Vector Integer Move Instructions
1775-
foreach vti = AllIntegerVectors in {
1780+
foreach vti = AllVectors in {
17761781
let Predicates = GetVTypePredicates<vti>.Predicates in {
1782+
def : Pat<(vti.Vector (riscv_vmv_v_v_vl (vti.Vector undef),
1783+
vti.RegClass:$rs2, VLOpFrag)),
1784+
(!cast<Instruction>("PseudoVMV_V_V_"#vti.LMul.MX)
1785+
vti.RegClass:$rs2, GPR:$vl, vti.Log2SEW)>;
1786+
def : Pat<(vti.Vector (riscv_vmv_v_v_vl vti.RegClass:$passthru,
1787+
vti.RegClass:$rs2, VLOpFrag)),
1788+
(!cast<Instruction>("PseudoVMV_V_V_"#vti.LMul.MX#"_TU")
1789+
vti.RegClass:$passthru, vti.RegClass:$rs2, GPR:$vl, vti.Log2SEW)>;
1790+
}
1791+
1792+
foreach vti = AllIntegerVectors in {
17771793
def : Pat<(vti.Vector (riscv_vmv_v_x_vl (vti.Vector undef), GPR:$rs2, VLOpFrag)),
17781794
(!cast<Instruction>("PseudoVMV_V_X_"#vti.LMul.MX)
17791795
GPR:$rs2, GPR:$vl, vti.Log2SEW)>;

‎llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -473,7 +473,7 @@ define <vscale x 6 x half> @extract_nxv6f16_nxv12f16_6(<vscale x 12 x half> %in)
473473
; CHECK-NEXT: vslidedown.vx v11, v10, a0
474474
; CHECK-NEXT: vslidedown.vx v8, v9, a0
475475
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma
476-
; CHECK-NEXT: vslideup.vi v9, v11, 0
476+
; CHECK-NEXT: vmv.v.v v9, v11
477477
; CHECK-NEXT: add a1, a0, a0
478478
; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, ma
479479
; CHECK-NEXT: vslideup.vx v8, v10, a0

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1433,7 +1433,7 @@ define <4 x i1> @pass_vector_mask_arg_via_stack(<4 x i1> %v) {
14331433
; LMULMAX8-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
14341434
; LMULMAX8-NEXT: vmv.v.i v17, 0
14351435
; LMULMAX8-NEXT: vsetivli zero, 4, e8, mf2, tu, ma
1436-
; LMULMAX8-NEXT: vslideup.vi v17, v16, 0
1436+
; LMULMAX8-NEXT: vmv.v.v v17, v16
14371437
; LMULMAX8-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
14381438
; LMULMAX8-NEXT: vmsne.vi v16, v17, 0
14391439
; LMULMAX8-NEXT: addi a0, sp, 136
@@ -1471,7 +1471,7 @@ define <4 x i1> @pass_vector_mask_arg_via_stack(<4 x i1> %v) {
14711471
; LMULMAX4-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
14721472
; LMULMAX4-NEXT: vmv.v.i v13, 0
14731473
; LMULMAX4-NEXT: vsetivli zero, 4, e8, mf2, tu, ma
1474-
; LMULMAX4-NEXT: vslideup.vi v13, v12, 0
1474+
; LMULMAX4-NEXT: vmv.v.v v13, v12
14751475
; LMULMAX4-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
14761476
; LMULMAX4-NEXT: vmsne.vi v12, v13, 0
14771477
; LMULMAX4-NEXT: addi a0, sp, 136
@@ -1515,7 +1515,7 @@ define <4 x i1> @pass_vector_mask_arg_via_stack(<4 x i1> %v) {
15151515
; LMULMAX2-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
15161516
; LMULMAX2-NEXT: vmv.v.i v11, 0
15171517
; LMULMAX2-NEXT: vsetivli zero, 4, e8, mf2, tu, ma
1518-
; LMULMAX2-NEXT: vslideup.vi v11, v10, 0
1518+
; LMULMAX2-NEXT: vmv.v.v v11, v10
15191519
; LMULMAX2-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
15201520
; LMULMAX2-NEXT: vmsne.vi v10, v11, 0
15211521
; LMULMAX2-NEXT: addi a0, sp, 136
@@ -1571,7 +1571,7 @@ define <4 x i1> @pass_vector_mask_arg_via_stack(<4 x i1> %v) {
15711571
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
15721572
; LMULMAX1-NEXT: vmv.v.i v10, 0
15731573
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, tu, ma
1574-
; LMULMAX1-NEXT: vslideup.vi v10, v9, 0
1574+
; LMULMAX1-NEXT: vmv.v.v v10, v9
15751575
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
15761576
; LMULMAX1-NEXT: vmsne.vi v9, v10, 0
15771577
; LMULMAX1-NEXT: addi a0, sp, 136

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extload-truncstore.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -536,7 +536,7 @@ define void @truncstore_v2i8_v2i1(<2 x i8> %x, ptr %z) {
536536
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
537537
; CHECK-NEXT: vmv.v.i v9, 0
538538
; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, ma
539-
; CHECK-NEXT: vslideup.vi v9, v8, 0
539+
; CHECK-NEXT: vmv.v.v v9, v8
540540
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
541541
; CHECK-NEXT: vmsne.vi v8, v9, 0
542542
; CHECK-NEXT: vsm.v v8, (a0)

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -347,7 +347,7 @@ define void @extract_v2i1_v64i1_0(ptr %x, ptr %y) {
347347
; LMULMAX2-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
348348
; LMULMAX2-NEXT: vmv.v.i v9, 0
349349
; LMULMAX2-NEXT: vsetivli zero, 2, e8, mf2, tu, ma
350-
; LMULMAX2-NEXT: vslideup.vi v9, v8, 0
350+
; LMULMAX2-NEXT: vmv.v.v v9, v8
351351
; LMULMAX2-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
352352
; LMULMAX2-NEXT: vmsne.vi v8, v9, 0
353353
; LMULMAX2-NEXT: vsm.v v8, (a1)
@@ -363,7 +363,7 @@ define void @extract_v2i1_v64i1_0(ptr %x, ptr %y) {
363363
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
364364
; LMULMAX1-NEXT: vmv.v.i v9, 0
365365
; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf2, tu, ma
366-
; LMULMAX1-NEXT: vslideup.vi v9, v8, 0
366+
; LMULMAX1-NEXT: vmv.v.v v9, v8
367367
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
368368
; LMULMAX1-NEXT: vmsne.vi v8, v9, 0
369369
; LMULMAX1-NEXT: vsm.v v8, (a1)
@@ -391,7 +391,7 @@ define void @extract_v2i1_v64i1_2(ptr %x, ptr %y) {
391391
; LMULMAX2-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
392392
; LMULMAX2-NEXT: vmv.v.i v9, 0
393393
; LMULMAX2-NEXT: vsetivli zero, 2, e8, mf2, tu, ma
394-
; LMULMAX2-NEXT: vslideup.vi v9, v8, 0
394+
; LMULMAX2-NEXT: vmv.v.v v9, v8
395395
; LMULMAX2-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
396396
; LMULMAX2-NEXT: vmsne.vi v8, v9, 0
397397
; LMULMAX2-NEXT: vsm.v v8, (a1)
@@ -412,7 +412,7 @@ define void @extract_v2i1_v64i1_2(ptr %x, ptr %y) {
412412
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
413413
; LMULMAX1-NEXT: vmv.v.i v9, 0
414414
; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf2, tu, ma
415-
; LMULMAX1-NEXT: vslideup.vi v9, v8, 0
415+
; LMULMAX1-NEXT: vmv.v.v v9, v8
416416
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
417417
; LMULMAX1-NEXT: vmsne.vi v8, v9, 0
418418
; LMULMAX1-NEXT: vsm.v v8, (a1)
@@ -441,7 +441,7 @@ define void @extract_v2i1_v64i1_42(ptr %x, ptr %y) {
441441
; LMULMAX2-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
442442
; LMULMAX2-NEXT: vmv.v.i v9, 0
443443
; LMULMAX2-NEXT: vsetivli zero, 2, e8, mf2, tu, ma
444-
; LMULMAX2-NEXT: vslideup.vi v9, v8, 0
444+
; LMULMAX2-NEXT: vmv.v.v v9, v8
445445
; LMULMAX2-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
446446
; LMULMAX2-NEXT: vmsne.vi v8, v9, 0
447447
; LMULMAX2-NEXT: vsm.v v8, (a1)
@@ -463,7 +463,7 @@ define void @extract_v2i1_v64i1_42(ptr %x, ptr %y) {
463463
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
464464
; LMULMAX1-NEXT: vmv.v.i v9, 0
465465
; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf2, tu, ma
466-
; LMULMAX1-NEXT: vslideup.vi v9, v8, 0
466+
; LMULMAX1-NEXT: vmv.v.v v9, v8
467467
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
468468
; LMULMAX1-NEXT: vmsne.vi v8, v9, 0
469469
; LMULMAX1-NEXT: vsm.v v8, (a1)
@@ -483,7 +483,7 @@ define void @extract_v2i1_nxv2i1_0(<vscale x 2 x i1> %x, ptr %y) {
483483
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
484484
; CHECK-NEXT: vmv.v.i v9, 0
485485
; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, ma
486-
; CHECK-NEXT: vslideup.vi v9, v8, 0
486+
; CHECK-NEXT: vmv.v.v v9, v8
487487
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
488488
; CHECK-NEXT: vmsne.vi v8, v9, 0
489489
; CHECK-NEXT: vsm.v v8, (a0)
@@ -508,7 +508,7 @@ define void @extract_v2i1_nxv2i1_2(<vscale x 2 x i1> %x, ptr %y) {
508508
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
509509
; CHECK-NEXT: vmv.v.i v9, 0
510510
; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, ma
511-
; CHECK-NEXT: vslideup.vi v9, v8, 0
511+
; CHECK-NEXT: vmv.v.v v9, v8
512512
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
513513
; CHECK-NEXT: vmsne.vi v8, v9, 0
514514
; CHECK-NEXT: vsm.v v8, (a0)
@@ -527,7 +527,7 @@ define void @extract_v2i1_nxv64i1_0(<vscale x 64 x i1> %x, ptr %y) {
527527
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
528528
; CHECK-NEXT: vmv.v.i v9, 0
529529
; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, ma
530-
; CHECK-NEXT: vslideup.vi v9, v8, 0
530+
; CHECK-NEXT: vmv.v.v v9, v8
531531
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
532532
; CHECK-NEXT: vmsne.vi v8, v9, 0
533533
; CHECK-NEXT: vsm.v v8, (a0)
@@ -552,7 +552,7 @@ define void @extract_v2i1_nxv64i1_2(<vscale x 64 x i1> %x, ptr %y) {
552552
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
553553
; CHECK-NEXT: vmv.v.i v9, 0
554554
; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, ma
555-
; CHECK-NEXT: vslideup.vi v9, v8, 0
555+
; CHECK-NEXT: vmv.v.v v9, v8
556556
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
557557
; CHECK-NEXT: vmsne.vi v8, v9, 0
558558
; CHECK-NEXT: vsm.v v8, (a0)
@@ -578,7 +578,7 @@ define void @extract_v2i1_nxv64i1_42(<vscale x 64 x i1> %x, ptr %y) {
578578
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
579579
; CHECK-NEXT: vmv.v.i v9, 0
580580
; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, ma
581-
; CHECK-NEXT: vslideup.vi v9, v8, 0
581+
; CHECK-NEXT: vmv.v.v v9, v8
582582
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
583583
; CHECK-NEXT: vmsne.vi v8, v9, 0
584584
; CHECK-NEXT: vsm.v v8, (a0)
@@ -603,7 +603,7 @@ define void @extract_v2i1_nxv32i1_26(<vscale x 32 x i1> %x, ptr %y) {
603603
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
604604
; CHECK-NEXT: vmv.v.i v9, 0
605605
; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, ma
606-
; CHECK-NEXT: vslideup.vi v9, v8, 0
606+
; CHECK-NEXT: vmv.v.v v9, v8
607607
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
608608
; CHECK-NEXT: vmsne.vi v8, v9, 0
609609
; CHECK-NEXT: vsm.v v8, (a0)

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