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[RISCV] Add riscv32 RUN lines to bittest.ll. NFC
Add extra check-prefixes to merge common results.
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‎llvm/test/CodeGen/RISCV/bittest.ll

Lines changed: 99 additions & 75 deletions
Original file line numberDiff line numberDiff line change
@@ -1,126 +1,135 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2+
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
3+
; RUN: | FileCheck %s -check-prefixes=CHECK,NOZBS,RV32,RV32I
24
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
3-
; RUN: | FileCheck %s -check-prefix=RV64I
5+
; RUN: | FileCheck %s -check-prefixes=CHECK,NOZBS,RV64,RV64I
6+
; RUN: llc -mtriple=riscv32 -mattr=+zbs -verify-machineinstrs < %s \
7+
; RUN: | FileCheck %s -check-prefixes=CHECK,ZBS,RV32,RV32ZBS
48
; RUN: llc -mtriple=riscv64 -mattr=+zbs -verify-machineinstrs < %s \
5-
; RUN: | FileCheck %s -check-prefix=RV64ZBS
9+
; RUN: | FileCheck %s -check-prefixes=CHECK,ZBS,RV64,RV64ZBS
610

711
define signext i32 @bittest_7_i32(i32 signext %a) nounwind {
8-
; RV64I-LABEL: bittest_7_i32:
9-
; RV64I: # %bb.0:
10-
; RV64I-NEXT: andi a0, a0, 128
11-
; RV64I-NEXT: seqz a0, a0
12-
; RV64I-NEXT: ret
13-
;
14-
; RV64ZBS-LABEL: bittest_7_i32:
15-
; RV64ZBS: # %bb.0:
16-
; RV64ZBS-NEXT: andi a0, a0, 128
17-
; RV64ZBS-NEXT: seqz a0, a0
18-
; RV64ZBS-NEXT: ret
12+
; CHECK-LABEL: bittest_7_i32:
13+
; CHECK: # %bb.0:
14+
; CHECK-NEXT: andi a0, a0, 128
15+
; CHECK-NEXT: seqz a0, a0
16+
; CHECK-NEXT: ret
1917
%shr = lshr i32 %a, 7
2018
%not = xor i32 %shr, -1
2119
%and = and i32 %not, 1
2220
ret i32 %and
2321
}
2422

2523
define signext i32 @bittest_10_i32(i32 signext %a) nounwind {
26-
; RV64I-LABEL: bittest_10_i32:
27-
; RV64I: # %bb.0:
28-
; RV64I-NEXT: andi a0, a0, 1024
29-
; RV64I-NEXT: seqz a0, a0
30-
; RV64I-NEXT: ret
31-
;
32-
; RV64ZBS-LABEL: bittest_10_i32:
33-
; RV64ZBS: # %bb.0:
34-
; RV64ZBS-NEXT: andi a0, a0, 1024
35-
; RV64ZBS-NEXT: seqz a0, a0
36-
; RV64ZBS-NEXT: ret
24+
; CHECK-LABEL: bittest_10_i32:
25+
; CHECK: # %bb.0:
26+
; CHECK-NEXT: andi a0, a0, 1024
27+
; CHECK-NEXT: seqz a0, a0
28+
; CHECK-NEXT: ret
3729
%shr = lshr i32 %a, 10
3830
%not = xor i32 %shr, -1
3931
%and = and i32 %not, 1
4032
ret i32 %and
4133
}
4234

4335
define signext i32 @bittest_11_i32(i32 signext %a) nounwind {
44-
; RV64I-LABEL: bittest_11_i32:
45-
; RV64I: # %bb.0:
46-
; RV64I-NEXT: srli a0, a0, 11
47-
; RV64I-NEXT: not a0, a0
48-
; RV64I-NEXT: andi a0, a0, 1
49-
; RV64I-NEXT: ret
36+
; NOZBS-LABEL: bittest_11_i32:
37+
; NOZBS: # %bb.0:
38+
; NOZBS-NEXT: srli a0, a0, 11
39+
; NOZBS-NEXT: not a0, a0
40+
; NOZBS-NEXT: andi a0, a0, 1
41+
; NOZBS-NEXT: ret
5042
;
51-
; RV64ZBS-LABEL: bittest_11_i32:
52-
; RV64ZBS: # %bb.0:
53-
; RV64ZBS-NEXT: bexti a0, a0, 11
54-
; RV64ZBS-NEXT: xori a0, a0, 1
55-
; RV64ZBS-NEXT: ret
43+
; ZBS-LABEL: bittest_11_i32:
44+
; ZBS: # %bb.0:
45+
; ZBS-NEXT: bexti a0, a0, 11
46+
; ZBS-NEXT: xori a0, a0, 1
47+
; ZBS-NEXT: ret
5648
%shr = lshr i32 %a, 11
5749
%not = xor i32 %shr, -1
5850
%and = and i32 %not, 1
5951
ret i32 %and
6052
}
6153

6254
define signext i32 @bittest_31_i32(i32 signext %a) nounwind {
63-
; RV64I-LABEL: bittest_31_i32:
64-
; RV64I: # %bb.0:
65-
; RV64I-NEXT: not a0, a0
66-
; RV64I-NEXT: srliw a0, a0, 31
67-
; RV64I-NEXT: ret
55+
; RV32-LABEL: bittest_31_i32:
56+
; RV32: # %bb.0:
57+
; RV32-NEXT: not a0, a0
58+
; RV32-NEXT: srli a0, a0, 31
59+
; RV32-NEXT: ret
6860
;
69-
; RV64ZBS-LABEL: bittest_31_i32:
70-
; RV64ZBS: # %bb.0:
71-
; RV64ZBS-NEXT: not a0, a0
72-
; RV64ZBS-NEXT: srliw a0, a0, 31
73-
; RV64ZBS-NEXT: ret
61+
; RV64-LABEL: bittest_31_i32:
62+
; RV64: # %bb.0:
63+
; RV64-NEXT: not a0, a0
64+
; RV64-NEXT: srliw a0, a0, 31
65+
; RV64-NEXT: ret
7466
%shr = lshr i32 %a, 31
7567
%not = xor i32 %shr, -1
7668
%and = and i32 %not, 1
7769
ret i32 %and
7870
}
7971

8072
define i64 @bittest_7_i64(i64 %a) nounwind {
81-
; RV64I-LABEL: bittest_7_i64:
82-
; RV64I: # %bb.0:
83-
; RV64I-NEXT: andi a0, a0, 128
84-
; RV64I-NEXT: seqz a0, a0
85-
; RV64I-NEXT: ret
73+
; RV32-LABEL: bittest_7_i64:
74+
; RV32: # %bb.0:
75+
; RV32-NEXT: andi a0, a0, 128
76+
; RV32-NEXT: seqz a0, a0
77+
; RV32-NEXT: li a1, 0
78+
; RV32-NEXT: ret
8679
;
87-
; RV64ZBS-LABEL: bittest_7_i64:
88-
; RV64ZBS: # %bb.0:
89-
; RV64ZBS-NEXT: andi a0, a0, 128
90-
; RV64ZBS-NEXT: seqz a0, a0
91-
; RV64ZBS-NEXT: ret
80+
; RV64-LABEL: bittest_7_i64:
81+
; RV64: # %bb.0:
82+
; RV64-NEXT: andi a0, a0, 128
83+
; RV64-NEXT: seqz a0, a0
84+
; RV64-NEXT: ret
9285
%shr = lshr i64 %a, 7
9386
%not = xor i64 %shr, -1
9487
%and = and i64 %not, 1
9588
ret i64 %and
9689
}
9790

9891
define i64 @bittest_10_i64(i64 %a) nounwind {
99-
; RV64I-LABEL: bittest_10_i64:
100-
; RV64I: # %bb.0:
101-
; RV64I-NEXT: andi a0, a0, 1024
102-
; RV64I-NEXT: seqz a0, a0
103-
; RV64I-NEXT: ret
92+
; RV32-LABEL: bittest_10_i64:
93+
; RV32: # %bb.0:
94+
; RV32-NEXT: andi a0, a0, 1024
95+
; RV32-NEXT: seqz a0, a0
96+
; RV32-NEXT: li a1, 0
97+
; RV32-NEXT: ret
10498
;
105-
; RV64ZBS-LABEL: bittest_10_i64:
106-
; RV64ZBS: # %bb.0:
107-
; RV64ZBS-NEXT: andi a0, a0, 1024
108-
; RV64ZBS-NEXT: seqz a0, a0
109-
; RV64ZBS-NEXT: ret
99+
; RV64-LABEL: bittest_10_i64:
100+
; RV64: # %bb.0:
101+
; RV64-NEXT: andi a0, a0, 1024
102+
; RV64-NEXT: seqz a0, a0
103+
; RV64-NEXT: ret
110104
%shr = lshr i64 %a, 10
111105
%not = xor i64 %shr, -1
112106
%and = and i64 %not, 1
113107
ret i64 %and
114108
}
115109

116110
define i64 @bittest_11_i64(i64 %a) nounwind {
111+
; RV32I-LABEL: bittest_11_i64:
112+
; RV32I: # %bb.0:
113+
; RV32I-NEXT: srli a0, a0, 11
114+
; RV32I-NEXT: not a0, a0
115+
; RV32I-NEXT: andi a0, a0, 1
116+
; RV32I-NEXT: li a1, 0
117+
; RV32I-NEXT: ret
118+
;
117119
; RV64I-LABEL: bittest_11_i64:
118120
; RV64I: # %bb.0:
119121
; RV64I-NEXT: srli a0, a0, 11
120122
; RV64I-NEXT: not a0, a0
121123
; RV64I-NEXT: andi a0, a0, 1
122124
; RV64I-NEXT: ret
123125
;
126+
; RV32ZBS-LABEL: bittest_11_i64:
127+
; RV32ZBS: # %bb.0:
128+
; RV32ZBS-NEXT: bexti a0, a0, 11
129+
; RV32ZBS-NEXT: xori a0, a0, 1
130+
; RV32ZBS-NEXT: li a1, 0
131+
; RV32ZBS-NEXT: ret
132+
;
124133
; RV64ZBS-LABEL: bittest_11_i64:
125134
; RV64ZBS: # %bb.0:
126135
; RV64ZBS-NEXT: bexti a0, a0, 11
@@ -133,6 +142,13 @@ define i64 @bittest_11_i64(i64 %a) nounwind {
133142
}
134143

135144
define i64 @bittest_31_i64(i64 %a) nounwind {
145+
; RV32-LABEL: bittest_31_i64:
146+
; RV32: # %bb.0:
147+
; RV32-NEXT: not a0, a0
148+
; RV32-NEXT: srli a0, a0, 31
149+
; RV32-NEXT: li a1, 0
150+
; RV32-NEXT: ret
151+
;
136152
; RV64I-LABEL: bittest_31_i64:
137153
; RV64I: # %bb.0:
138154
; RV64I-NEXT: srli a0, a0, 31
@@ -152,6 +168,13 @@ define i64 @bittest_31_i64(i64 %a) nounwind {
152168
}
153169

154170
define i64 @bittest_32_i64(i64 %a) nounwind {
171+
; RV32-LABEL: bittest_32_i64:
172+
; RV32: # %bb.0:
173+
; RV32-NEXT: not a0, a1
174+
; RV32-NEXT: andi a0, a0, 1
175+
; RV32-NEXT: li a1, 0
176+
; RV32-NEXT: ret
177+
;
155178
; RV64I-LABEL: bittest_32_i64:
156179
; RV64I: # %bb.0:
157180
; RV64I-NEXT: srli a0, a0, 32
@@ -171,17 +194,18 @@ define i64 @bittest_32_i64(i64 %a) nounwind {
171194
}
172195

173196
define i64 @bittest_63_i64(i64 %a) nounwind {
174-
; RV64I-LABEL: bittest_63_i64:
175-
; RV64I: # %bb.0:
176-
; RV64I-NEXT: not a0, a0
177-
; RV64I-NEXT: srli a0, a0, 63
178-
; RV64I-NEXT: ret
197+
; RV32-LABEL: bittest_63_i64:
198+
; RV32: # %bb.0:
199+
; RV32-NEXT: not a0, a1
200+
; RV32-NEXT: srli a0, a0, 31
201+
; RV32-NEXT: li a1, 0
202+
; RV32-NEXT: ret
179203
;
180-
; RV64ZBS-LABEL: bittest_63_i64:
181-
; RV64ZBS: # %bb.0:
182-
; RV64ZBS-NEXT: not a0, a0
183-
; RV64ZBS-NEXT: srli a0, a0, 63
184-
; RV64ZBS-NEXT: ret
204+
; RV64-LABEL: bittest_63_i64:
205+
; RV64: # %bb.0:
206+
; RV64-NEXT: not a0, a0
207+
; RV64-NEXT: srli a0, a0, 63
208+
; RV64-NEXT: ret
185209
%shr = lshr i64 %a, 63
186210
%not = xor i64 %shr, -1
187211
%and = and i64 %not, 1

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