Skip to content

Commit 1889d8d

Browse files
Dinar TemirbulatovDinar Temirbulatov
Dinar Temirbulatov
authored and
Dinar Temirbulatov
committed
Resolved remarks.
1 parent 9705cee commit 1889d8d

File tree

3 files changed

+49
-27
lines changed

3 files changed

+49
-27
lines changed

‎llvm/lib/Target/AArch64/AArch64InstrInfo.td

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -740,6 +740,8 @@ def AArch64vsli : SDNode<"AArch64ISD::VSLI", SDT_AArch64vshiftinsert>;
740740
def AArch64vsri : SDNode<"AArch64ISD::VSRI", SDT_AArch64vshiftinsert>;
741741

742742
def AArch64bsp: SDNode<"AArch64ISD::BSP", SDT_AArch64trivec>;
743+
def AArch64nbsl: PatFrag<(ops node:$Op1, node:$Op2, node:$Op3),
744+
(vnot (AArch64bsp node:$Op1, node:$Op2, node:$Op3))>;
743745

744746
def AArch64cmeq: SDNode<"AArch64ISD::CMEQ", SDT_AArch64binvec>;
745747
def AArch64cmge: SDNode<"AArch64ISD::CMGE", SDT_AArch64binvec>;

‎llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td

Lines changed: 1 addition & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -3760,30 +3760,13 @@ let Predicates = [HasSVE2orSME] in {
37603760
defm BSL_ZZZZ : sve2_int_bitwise_ternary_op<0b001, "bsl", int_aarch64_sve_bsl, AArch64bsp>;
37613761
defm BSL1N_ZZZZ : sve2_int_bitwise_ternary_op<0b011, "bsl1n", int_aarch64_sve_bsl1n>;
37623762
defm BSL2N_ZZZZ : sve2_int_bitwise_ternary_op<0b101, "bsl2n", int_aarch64_sve_bsl2n>;
3763-
defm NBSL_ZZZZ : sve2_int_bitwise_ternary_op<0b111, "nbsl", int_aarch64_sve_nbsl>;
3763+
defm NBSL_ZZZZ : sve2_int_bitwise_ternary_op<0b111, "nbsl", int_aarch64_sve_nbsl, AArch64nbsl>;
37643764

37653765
// SVE2 bitwise xor and rotate right by immediate
37663766
defm XAR_ZZZI : sve2_int_rotate_right_imm<"xar", int_aarch64_sve_xar>;
37673767

37683768
// SVE2 extract vector (immediate offset, constructive)
37693769
def EXT_ZZI_B : sve2_int_perm_extract_i_cons<"ext">;
3770-
3771-
// zext(cmpeq(bsl(x, y, z), splat(0))) -> nbsl(x, y, z)
3772-
def : Pat<(nxv16i8 (zext (nxv16i1 (AArch64setcc_z (nxv16i1 (SVEAllActive)),
3773-
(nxv16i8 (AArch64bsp nxv16i8:$Op1, nxv16i8:$Op2, nxv16i8:$Op3)), (SVEDup0), SETEQ)))),
3774-
(NBSL_ZZZZ nxv16i8:$Op1, nxv16i8:$Op2, nxv16i8:$Op3)>;
3775-
3776-
def : Pat<(nxv8i16 (zext (nxv8i1 (AArch64setcc_z (nxv8i1 (SVEAllActive)),
3777-
(nxv8i16 (AArch64bsp nxv8i16:$Op1, nxv8i16:$Op2, nxv8i16:$Op3)), (SVEDup0), SETEQ)))),
3778-
(NBSL_ZZZZ nxv8i16:$Op1, nxv8i16:$Op2, nxv8i16:$Op3)>;
3779-
3780-
def : Pat<(nxv4i32 (zext (nxv4i1 (AArch64setcc_z (nxv4i1 (SVEAllActive)),
3781-
(nxv4i32 (AArch64bsp nxv4i32:$Op1, nxv4i32:$Op2, nxv4i32:$Op3)), (SVEDup0), SETEQ)))),
3782-
(NBSL_ZZZZ nxv4i32:$Op1, nxv4i32:$Op2, nxv4i32:$Op3)>;
3783-
3784-
def : Pat<(nxv2i64 (zext (nxv2i1 (AArch64setcc_z (nxv2i1 (SVEAllActive)),
3785-
(nxv2i64 (AArch64bsp nxv2i64:$Op1, nxv2i64:$Op2, nxv2i64:$Op3)), (SVEDup0), SETEQ)))),
3786-
(NBSL_ZZZZ nxv2i64:$Op1, nxv2i64:$Op2, nxv2i64:$Op3)>;
37873770
} // End HasSVE2orSME
37883771

37893772
let Predicates = [HasSVE2] in {

‎llvm/test/CodeGen/AArch64/sve2-bsl.ll

Lines changed: 46 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -42,17 +42,54 @@ define <vscale x 4 x i32> @no_bsl_fold(<vscale x 4 x i32> %a, <vscale x 4 x i32>
4242
ret <vscale x 4 x i32> %c
4343
}
4444

45-
define <vscale x 4 x i32> @nbsl(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
46-
; CHECK-LABEL: nbsl:
45+
define <vscale x 16 x i8> @nbsl_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
46+
; CHECK-LABEL: nbsl_i8:
47+
; CHECK: // %bb.0:
48+
; CHECK-NEXT: mov z2.b, #127 // =0x7f
49+
; CHECK-NEXT: nbsl z0.d, z0.d, z1.d, z2.d
50+
; CHECK-NEXT: ret
51+
%1 = and <vscale x 16 x i8> %a, splat(i8 127)
52+
%2 = and <vscale x 16 x i8> %b, splat(i8 -128)
53+
%3 = or <vscale x 16 x i8> %1, %2
54+
%4 = xor <vscale x 16 x i8> %3, splat(i8 -1)
55+
ret <vscale x 16 x i8> %4
56+
}
57+
58+
define <vscale x 8 x i16> @nbsl_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
59+
; CHECK-LABEL: nbsl_i16:
60+
; CHECK: // %bb.0:
61+
; CHECK-NEXT: mov z2.h, #32767 // =0x7fff
62+
; CHECK-NEXT: nbsl z0.d, z0.d, z1.d, z2.d
63+
; CHECK-NEXT: ret
64+
%1 = and <vscale x 8 x i16> %a, splat(i16 32767)
65+
%2 = and <vscale x 8 x i16> %b, splat(i16 -32768)
66+
%3 = or <vscale x 8 x i16> %1, %2
67+
%4 = xor <vscale x 8 x i16> %3, splat(i16 -1)
68+
ret <vscale x 8 x i16> %4
69+
}
70+
71+
define <vscale x 4 x i32> @nbsl_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
72+
; CHECK-LABEL: nbsl_i32:
4773
; CHECK: // %bb.0:
4874
; CHECK-NEXT: mov z2.s, #0x7fffffff
49-
; CHECK-NEXT: nbsl z2.d, z2.d, z0.d, z1.d
50-
; CHECK-NEXT: mov z0.d, z2.d
75+
; CHECK-NEXT: nbsl z0.d, z0.d, z1.d, z2.d
5176
; CHECK-NEXT: ret
52-
%1 = and <vscale x 4 x i32> %a, shufflevector (<vscale x 4 x i32> insertelement (<vscale x 4 x i32> poison, i32 2147483647, i64 0), <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer)
53-
%2 = and <vscale x 4 x i32> %b, shufflevector (<vscale x 4 x i32> insertelement (<vscale x 4 x i32> poison, i32 -2147483648, i64 0), <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer)
77+
%1 = and <vscale x 4 x i32> %a, splat(i32 2147483647)
78+
%2 = and <vscale x 4 x i32> %b, splat(i32 -2147483648)
5479
%3 = or <vscale x 4 x i32> %1, %2
55-
%4 = icmp eq <vscale x 4 x i32> %3, zeroinitializer
56-
%5 = zext <vscale x 4 x i1> %4 to <vscale x 4 x i32>
57-
ret <vscale x 4 x i32> %5
80+
%4 = xor <vscale x 4 x i32> %3, splat(i32 -1)
81+
ret <vscale x 4 x i32> %4
82+
}
83+
84+
define <vscale x 2 x i64> @nbsl_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
85+
; CHECK-LABEL: nbsl_i64:
86+
; CHECK: // %bb.0:
87+
; CHECK-NEXT: mov z2.d, #0x7fffffffffffffff
88+
; CHECK-NEXT: nbsl z0.d, z0.d, z1.d, z2.d
89+
; CHECK-NEXT: ret
90+
%1 = and <vscale x 2 x i64> %a, splat(i64 9223372036854775807)
91+
%2 = and <vscale x 2 x i64> %b, splat(i64 -9223372036854775808)
92+
%3 = or <vscale x 2 x i64> %1, %2
93+
%4 = xor <vscale x 2 x i64> %3, splat(i64 -1)
94+
ret <vscale x 2 x i64> %4
5895
}

0 commit comments

Comments
 (0)