address comments

Author: AlexMaclean

llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp

@@ -68,7 +68,7 @@ bool NVPTXDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
 
 NVPTX::DivPrecisionLevel
 NVPTXDAGToDAGISel::getDivF32Level(const SDNode *N) const {
-  return Subtarget->getTargetLowering()->getDivF32Level(*MF, N);
+  return Subtarget->getTargetLowering()->getDivF32Level(*MF, *N);
 }
 
 bool NVPTXDAGToDAGISel::usePrecSqrtF32() const {

llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp

@@ -116,7 +116,7 @@ static cl::opt<bool> ForceMinByValParamAlign(
 
 NVPTX::DivPrecisionLevel
 NVPTXTargetLowering::getDivF32Level(const MachineFunction &MF,
-                                    const SDNode *N) const {
+                                    const SDNode &N) const {
   // If nvptx-prec-div32=N is used on the command-line, always honor it
   if (UsePrecDivF32.getNumOccurrences() > 0)
     return UsePrecDivF32;
@@ -125,11 +125,9 @@ NVPTXTargetLowering::getDivF32Level(const MachineFunction &MF,
   if (allowUnsafeFPMath(MF))
     return NVPTX::DivPrecisionLevel::Approx;
 
-  if (N) {
-    const SDNodeFlags Flags = N->getFlags();
-    if (Flags.hasApproximateFuncs())
-      return NVPTX::DivPrecisionLevel::Approx;
-  }
+  const SDNodeFlags Flags = N.getFlags();
+  if (Flags.hasApproximateFuncs())
+    return NVPTX::DivPrecisionLevel::Approx;
 
   return NVPTX::DivPrecisionLevel::IEEE754;
 }

llvm/lib/Target/NVPTX/NVPTXISelLowering.h

@@ -217,7 +217,7 @@ class NVPTXTargetLowering : public TargetLowering {
   // Get the degree of precision we want from 32-bit floating point division
   // operations.
   NVPTX::DivPrecisionLevel getDivF32Level(const MachineFunction &MF,
-                                          const SDNode *N) const;
+                                          const SDNode &N) const;
 
   // Get whether we should use a precise or approximate 32-bit floating point
   // sqrt instruction.

llvm/lib/Target/NVPTX/NVPTXInstrInfo.td

@@ -1294,7 +1294,7 @@ def FDIV32ri :
 //
 // F32 Accurate reciprocal
 //
-def FDIV321r_prec_ftz :
+def FRCP32r_prec_ftz :
   NVPTXInst<(outs Float32Regs:$dst),
             (ins Float32Regs:$b),
             "rcp.rn.ftz.f32 \t$dst, $b;",